Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
Low-Latency ASIC Algorithms of Modular Squaring of Large Integers for VDF Evaluation
TL;DR: In this paper , the authors propose a class of modular squaring algorithms suitable for low-latency ASIC implementations, which achieve highest levels of parallelization that have not been explored in previous works in the literature.
Power-aware design of MCML logarithmic adders
TL;DR: Results of simulations indicate that the proposed methodology offers a good starting point before fine-tuning the design by SPICE simulations, and the tradeoff that can be realized between performance and power consumption is discussed.
Posted Content
Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Two
Stephan Held,Sophie Spirkl +1 more
TL;DR: This article integrates the individual advantages of all previous adder circuits into a new family of full adders, the first to improve on the depth bound of 2 log2n while maintaining a fan-out bound of two and achieves an asymptotically optimum logic gate depth of log 2n + o(log 2n) and linear size O(n).
Proceedings ArticleDOI
DSP architecture with folded tree for power constraint devices
TL;DR: Carry look-ahead adder is replaced by LFA and PA to harness the energy depleted in an application (e.g., DSP application) and power consumption is reduced by 12-15% as compared with the existing algorithms using Cyclone III (EP3C16F484C6).
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.