Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
Residue Arithmetic A Tutorial with Examples
TL;DR: One of the common rules of converting remainders, or residues, into integers as the Chinese Remainder Theorem, or CRT is referred to as the CRT today.
Journal ArticleDOI
Design space exploration for 3D architectures
TL;DR: A brief introduction to 3D integration technology is given, the EDA design tools that can enable the adoption of 3D ICs are discussed, and the implementation of various microprocessor components using 3D technology is presented.
Proceedings ArticleDOI
Fast area-efficient VLSI adders
Tackdon Han,David A. Carlson +1 more
TL;DR: A new graph representation for prefix computation is presented that leads to the design of a fast, area-efficient binary adder, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs.
Proceedings ArticleDOI
A family of adders
TL;DR: These are end cases of a large family of addition structures, all of which share the attractive property of minimum logical depth, and can thus usually achieve a more attractive combination of speed and area/power cost than either of the known end-cases.
Proceedings ArticleDOI
Variable latency speculative addition: a new paradigm for arithmetic circuit design
TL;DR: A novel adder design is presented that is exponentially faster than traditional adders; however, it produces incorrect results, deterministically, for a very small fraction of input combinations.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.