Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
Low-Area wallace multiplier
Shahzad Asif,Yinan Kong +1 more
TL;DR: Synthesis results show that the proposed multiplier has the lowest area as compared to other tree-based multipliers, without compromising on the speed of the original Wallace multiplier.
Patent
Modified wallace-tree adder for high-speed binary multiplier, structure and method
TL;DR: In this paper, a carry-save adder for use in a binary multiplier with a reduced number of full adder stages is proposed, which is implemented with a plurality of one-bit and two-bit full adders.
Journal ArticleDOI
The complexity of a VLSI adder
TL;DR: This note will develop a lower bound on the area-time complexity of binary addition, using very similar models of VLSI chips to find bounds on the complexity of various computations such as multiplication and discrete Fourier transformation.
Proceedings ArticleDOI
Area minimization algorithm for parallel prefix adders under bitwise delay constraints
Taeko Matsunaga,Yusuke Matsunaga +1 more
TL;DR: This paper addresses parallel prefix adder synthesis which targets area minimization under given timing constraints, and a two-folded robust heuristic is proposed, which removes imposed restrictions on structure, and restructures the result of DPAM for further area reduction.
Journal ArticleDOI
Serial Addition: Locally Connected Architectures
TL;DR: Analysis, backed by simulation results, on comparing parallel and serial addition shows that serial adders are more reliable while also dissipating less, and theory and simulations will support the claim that a serial adder is a very serious candidate for highly reliable and low power operations.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.