Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Effects of floating-point non-associativity on numerical computations on massively multithreaded systems
Oreste Villa,Daniel Chavarría-Miranda,Vidhya Gurumoorthi,Andres Marquez,Sriram Krishnamoorthy +4 more
TL;DR: Floating-point operations, as dened in the IEEE754 standard, are not associative, so the ordering of large numbers of operations that deal with operands of substantially different magnitudes can signicantly vary.
Proceedings ArticleDOI
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
TL;DR: An efficient algorithm to synthesize prefix graph structures that yield adders with the best performance-area trade-off and can handle more complex constraints such as maximum node fanout or wire-length that impact the performance/area of a design and generate several feasible solutions that minimize the objective function.
Book
Special purpose parallel computing
TL;DR: This paper presents a survey of various aspects of special purpose parallel computing system design, analysis, implementation and veriication in recent years.
Proceedings ArticleDOI
Algorithm transformations for unlimited parallelism
TL;DR: A unified algebraic basis for transforming algorithms to achieve unlimited parallelism is provided and a certain class of algebraic structures is shown to be sufficient for the application of the look-ahead computation of recursive algorithms.
Journal ArticleDOI
Mechanical Verification of Adder Circuits using Rewrite RuleLaboratory
Deepak Kapur,M. Subramaniam +1 more
TL;DR: There is strong evidence that the proposed methodology for generating proofs should scale up for large circuits exhibiting regularity that can be described using divide-and-conquer strategy in terms of powerlists.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.