Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
The VLSI Complexity of Sorting
TL;DR: The area-time complexity of sorting is analyzed under an updated model of VLSI computation, which makes a distinction between "processing" circuits and "memory" circuits; the latter are less important since they are denser and consume less power.
Proceedings ArticleDOI
Cost reduction and evaluation of a temporary faults detecting technique
Lorena Anghel,Michael Nicolaidis +1 more
TL;DR: The obtained results show that detection of such temporal faults can be achieved by means of meaningful hardware and performance cost.
Journal ArticleDOI
Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA
Vikramkumar Pudi,K. Sridharan +1 more
TL;DR: This paper derives bounds on the number of majority gates for -bit RCA and -bit Brent-Kung, Kogge-Stone, Ladner-Fischer, and Han-Carlson adders and uses these results to present efficient QCA designs for the ripple carry adder (RCA) and various prefix adders.
Proceedings ArticleDOI
A taxonomy of parallel prefix networks
TL;DR: A three-dimensional taxonomy is presented that not only describes the tradeoffs in existing parallel prefix networks but also points to a family of new networks that are competitive in latency and area for some technologies.
Journal ArticleDOI
High performance and scalable radix sorting: a case study of implementing dynamic parallelism for gpu computing
Duane Merrill,Andrew S. Grimshaw +1 more
TL;DR: A family of very efficient parallel algorithms for radix sorting; and the authors' allocation-oriented algorithmic design strategies that match the strengths of GPU processor architecture to this genre of dynamic parallelism are presented.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.