Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings ArticleDOI
3D CMOS SOI for high performance computing
TL;DR: A new three-dimensional CMOS-SOI technology is presented, design methodologies are proposed for this technology and last, a comparison is carried out between 2D and 3D designs.
Proceedings ArticleDOI
Incremental-in-time algorithm for digital simulation
TL;DR: The authors present an incremental-in-time algorithm for incremental simulation of digital circuits that maximally utilizes the past history, thereby reducing the number of component evaluations to a minimum.
Journal ArticleDOI
A new approach to constructing optimal parallel prefix circuits with small depth
Yen-Chun Lin,Jun-Wei Hsiao +1 more
TL;DR: A new approach to easing the design of parallel prefix circuits is presented, and a depth-size optimum parallel prefix circuit, named WE4 with fan-out 4 is constructed, which has the smallest depth among all known depthsize optimal prefix circuits with bounded fan- out.
Journal ArticleDOI
Analysis and Design of Adders for Approximate Computing
TL;DR: This article proposes four Approximate Full Adders (AFAs) for high-performance energy-efficient approximate computing and exploits the concept of carry-lifetime and Error Detection and Correction logic, respectively, to improve ED and ER and introduces two more (improved) versions of ApproxADD.
Journal ArticleDOI
Systolic digit-serial multiplier
TL;DR: In this article, a new architecture for digit-serial multiplication is presented, where the delay in obtaining the least significant digit is independent of the number of digits and hence the word length.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.