Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
Efficient Algorithm and Fast Hardware Implementation for Multiply-by-(1+2 k )
Studying the Interplay of Concurrency, Performance, Energy and Reliability with ArchOn – an Architecture-open Resource-driven Cross-layer Modelling Framework
TL;DR: ArchOn as discussed by the authors is based on a resource-driven graph representation and facilitates the analysis and potentially design and synthesis of systems whose design domains are more conveniently organized into multiple layers or levels (e.g. application, OS, hardware, etc.) and potentially large scale and diverse types of concurrency.
Posted Content
Faster Quantum Concentration via Grover's Search.
Cem M. Unsal,A. Yavuz Oruç +1 more
TL;DR: In this paper, quantum algorithms for routing concentration assignments on full capacity concentrators, bounded fat-and-slim concentrators and regular fat and slim concentrators were presented, which are asymptotically faster than their classical counterparts.
Proceedings ArticleDOI
Towards Polynomial Formal Verification of AI-Generated Arithmetic Circuits
Rolf Drechsler,Alireza Mahzoon +1 more
TL;DR: In this paper , the complexity bounds for formal verification based on Binary Decision Diagrams (BDDs) when they are used to ensure the correctness of general prefix adders were investigated. And they proved that the PFV of a prefix adder is possible independent of the prefix tree structure.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.