Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
More filters
An In-Depth Look at Prior Art in Fast Round-Robin Arbiter Circuits
Hasan Fatih Uğurdağ,O. Baskirt +1 more
TL;DR: This paper presents an in-depth literature survey of previous work on round-robin arbitration, then defines the typical RRA problem (RRA_typical), and investigates work on fast architectures that solve the RRA_Typical problem.
Journal ArticleDOI
AritPIM: High-Throughput In-Memory Arithmetic
TL;DR: In this paper , the authors propose a state-of-the-art suite of arithmetic algorithms for adding, subtraction, multiplication, and division for both fixed-point and floating-point numbers using both bit serial and bit-parallel approaches.
Book ChapterDOI
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders
TL;DR: A novel bit-level algorithm is introduced that allows the design of power-efficient parallel-prefix adders and results reveal that the proposed adders achieve significant power reductions when compared to traditional parallel- prefix adders, while maintaining equal operation speed.
Proceedings ArticleDOI
Area-time efficient arithmetic elements for VLSI systems
TL;DR: Algorithms for the high speed binary arithmetic operations of addition and multiplication in a VLSI environment are analyzed for area-time efficiency and solutions that yield area- time efficient practical implementations of these arithmetic functions are described.
Journal ArticleDOI
Exploring scalable schedules for IIR filters with resource constraints
TL;DR: A novel approach, based on harmonic scheduling, that addresses the tradeoffs between resource constraints and the processing speed of the resulting schedules, which can be used to explore the design space of scalable parallel schedules implementing IIR filters with resource constraints is presented.
References
More filters
Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.