Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
Comparisons of Synchronous-Clocking SFQ Adders
Naofumi Takagi,Masamitsu Tanaka +1 more
TL;DR: This paper compares implementations of hardware algorithms for addition by synchronous-clocking SFQ circuits and shows that a set of individual bit-serial adders and Kogge-Stone adder are superior to others.
Dissertation
Architectures for Floating-Point Division
TL;DR: Thesis (Ph.D. as discussed by the authors ) at the University of Adelaide, School of Electrical and Electronic Engineering, 2005, was the first work to address the problem of wireless sensor networks.
Proceedings ArticleDOI
64-bit prefix adders: Power-efficient topologies and design solutions
TL;DR: The intrinsically sparser designs in hierarchical prefix scheme are demonstrated to be preferable choices for both high-performance and lowpower adder applications.
Comparison of Parallel Prefix Adder (PPA)
TL;DR: This project will compare and study the performances of these two adder in terms of propagation delay and design area based on different sizes of bits to show which of the two adders being tested perform better.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.