Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
The blackjack tutor chip
M. Weeks,B. Wilson,M. Bayoumi +2 more
TL;DR: Develops an application specific chip to advise a blackjack player on the next best move and indicates when the player has blackjack, whether the player should stay or draw, when thePlayer has "busted" and when the Player has given a bad value for the dealer's up card.
Journal ArticleDOI
Design and Implementation of Novel Multiplier using Barrel Shifters
Neeta Pandey,Saurabh Gupta +1 more
TL;DR: A design scheme to provide a faster implementation of multiplication of two signed or unsigned numbers using modified booth's algorithm in conjunction with barrel shifters and provides a uniform architecture which makes upgrading to a bigger multiplier much easier than other schemes.
Journal ArticleDOI
Parallel priority queues based on binomial heaps
Sajal K. Das,M. Cristina Pinotti +1 more
TL;DR: The main result is an interesting application of the parallel computation of carry bits in a full adder logic to binomial heaps, thus optimizing the parallel time complexity of the Union of two queues.
Patent
Conditionally cycle-free generalized tanner graphs based decoding
Thomas R. Halford,Keith M. Chugg +1 more
TL;DR: In this paper, a cyclic graphical model is used to represent a coding scheme associated with the received data units, and a cycle-free graphical model for a plurality of second conditions allowable by the coding scheme is obtained.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.