Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings ArticleDOI
Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design
Journal ArticleDOI
A 250-MHz wave pipelined adder in 2-/spl mu/m CMOS
TL;DR: A 16-b parallel adder, utilizing wave pipelining is implemented with MOSIS 2-/spl mu/m technology and test results of fabricated devices show more than nine times speedup over nonpipelined operation.
Journal ArticleDOI
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
TL;DR: A carry skip adder structure that has a higher speed yet lower energy consumption compared with the conventional one, and a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented.
Journal ArticleDOI
Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands
TL;DR: Five novel VLA architectures, based on Brent-Kung, Ladner-Fisher, Sklansky, Hybrid Han-Carlson, and Carry increment parallel-prefix topologies are proposed and results show that proposed VLAs outperform previous speculative architectures and standard (non-speculative) adders when high-speed is required.
Journal ArticleDOI
A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter
Yajuan He,Chip-Hong Chang +1 more
TL;DR: An efficient reverse converter for transforming the redundant binary representation into two's complement form that expends at least two times less energy than the competitor circuit and is capable of completing a 64-bit conversion in 829 ps and dissipates merely 5.84 mW.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.