Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings ArticleDOI
Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product
TL;DR: A first-order model is proposed to quickly analyze the general characteristics of the area-delay product and an algorithm is presented to construct an abstract structure for any logarithmic adder with a fanout of two.
A new approach to the design of optimal parallel prefix circuits
Mary Sheeran,Ian Parberry +1 more
TL;DR: A new construction, called Slices, for fan- out-constrained depth size optimal (DSO) parallel prefix circuits is presented, which encompasses the largest possible number of inputs for given depth and fan-out.
Proceedings ArticleDOI
Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic
TL;DR: The successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches is reported.
Proceedings ArticleDOI
A 3.5 ns, 64 bit, carry-lookahead adder
D. Dozza,M. Gaddoni,G. Baccarani +2 more
TL;DR: The adder has a novel array structure which represents a variant of the architecture suggested by Brent and Kung, however, it does not require the back propagation of the signals which is necessary for the intermediate carry bits; hence only log/sub 2/ n logic levels are employed for the generation of all the carry signals.
Patent
Logic gate having reduced power dissipation and method of operation thereof
TL;DR: In this article, a combinatorial logic power-down circuit was proposed for decreasing DC power dissipation in a logic gate and a processor incorporating the circuit or the method, where the logic gate has at least two binary inputs adapted to receive corresponding input binary digits.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.