Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings ArticleDOI
High-Speed Hybrid Parallel-Prefix Carry-Select Adder Using Ling's Algorithm
TL;DR: A novel technique of implementing a hybrid parallel- prefix ling adder and experimental results show that the proposed adder has an improvement of 63% in speed and about 13% reduction in power consumption compared to Carry Lookahead adder.
Proceedings ArticleDOI
Observation of one-fifth-of-a-clock wake-up time of power-gated circuit
TL;DR: The wake-up time of zigzag super cut-off CMOS (ZSCCMOS) is measured using a functional block for the first time and it is shown to be effective as a clock-gating substitute.
Journal ArticleDOI
Parallel prefix computation with few processors
Ömer Eǧecioǧlu,Çetin Kaya Koç +1 more
TL;DR: The algorithm is compared with the distributed-memory implementation of the parallel prefix algorithm proposed by Kruskal, Rudolph, and Snir and is shown to be more efficient when n is large and p 2 (p − 1) ≤ 4 τ .
Proceedings ArticleDOI
Design of High Speed Adders Using CMOS and Transmission Gates in Submicron Technology: A Comparative Study
Akansha Baliga,Deepa Yagain +1 more
TL;DR: This paper involves the design of high speed, parallel-prefix adders such as Brent-Kung, Sklansky, Kogge-Stone and Ling adders, by KogGE-Stone implementation, using CMOS logic and transmission gate logic.
Proceedings ArticleDOI
Exploring the use of parallel prefix adder topologies into approximate adder circuits
TL;DR: This paper evaluates the use of Brent-Kung, Kogge-Stone, Han Carlson, Ladner-Fisher, and Sklansky PPAs in the precise part of two well-known approximate adders, i.e., Error Tolerant Adder I (ETA-I) and Copy adder.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.