Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
More filters
Study and Design of a 32-bit High-Speed Adder
TL;DR: In this article, a tesi si propone di studiare e verificare il funzionamento delle principali topologie di sommatori (Ripple-Carry, Carry Lookahead) ad alta velocita.
Proceedings ArticleDOI
A 64-bit fast adder with 0.18 μm CMOS technology
TL;DR: The organization and circuit design of a 64-bit high speed binary parallel adder built in TSMC 2.5 V 0.18 mum IP6M CMOS fabrication technology is presented and the delay of each stage in the adder is reduced using clock-delayed domino logic.
Brief Contributions A Fast Radix-4 Division Algorithm and its Architecture
TL;DR: In this paper, a fast radix-4 division algorithm for floating point numbers is presented, which is based on Svoboda's division algorithm and the radix 4 redundant number system.
Book ChapterDOI
A Time Driven Adder Generator Architecture
TL;DR: The design and implementation of a time driven adder generator architecture that allows the parametrization of the architecture to fit ones design constraints is presented.
References
More filters
Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.