Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits
TL;DR: A high performance 32-bit adder is designed and is used as a benchmark for applying a low power technique without performance degradation, and a dual supply technique for compound domino logic is proposed and is implemented in the adder.
Proceedings ArticleDOI
A Novel Framework for Procedural Construction of Parallel Prefix Adders
TL;DR: “Join”, “insertion” and “interleaving” are introduced as basic operations for constructing feasible parallel prefix diagram (the core structure of a parallel prefix adder) in this paper, and it is demonstrated that well-known benchmark structures are all successfully decomposed/constructed in this novel framework.
Proceedings ArticleDOI
A fast optimal robust path delay fault testable adder
TL;DR: A lower bound of /spl omega/(n/sup 2/) for the cardinality of a complete test set for a combinational n-bit adder is proven and is valid for any adder design known until now.
Proceedings ArticleDOI
Memristor based adder circuit design
TL;DR: It is shown that the Kogge-Stone design has the best metric in terms of delay and area among the parallel prefix adders.
Proceedings ArticleDOI
A performance driven generator for efficient testable conditional-sum-adders
Bernd Becker,Paul Molitor +1 more
TL;DR: The authors present a performance driven generator for integer adders which is parameterized in n, the operands' bit length, t/sub n/, the delay of the addition, and FM, the (cell based static) fault model.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.