Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
A GHz MOS adaptive pipeline technique using MOS current-mode logic
Masayuki Mizuno,Masakazu Yamashina,Koichiro Furuta,H. Igura,Hitoshi Abiko,K. Okabe,Atsuki Ono,Hachiro Yamada +7 more
TL;DR: An adaptive pipeline (APL) technique is described, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations, and it is shown that MOS current-mode logic circuits are suitable for a low-noise variable delay circuit.
Journal ArticleDOI
High-speed parallel-prefix VLSI Ling adders
TL;DR: Experimental results reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the fastest parallel-prefix architectures presented for the traditional definition of carry equations.
Journal ArticleDOI
Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications
TL;DR: A comprehensive survey and a comparative evaluation of recently developed approximate arithmetic circuits under different design constraints, synthesized and characterized under optimizations for performance and area.
Journal ArticleDOI
Diminished-one modulo 2/sup n/+1 adder design
TL;DR: In this paper, the authors present two new design methodologies for modulo 2/sup n/1 addition in the diminished-one number system, the first leads to carry look-ahead, whereas the second to parallel-prefix adder implementations.
Journal ArticleDOI
Threshold logic circuit design of parallel adders using resonant tunneling devices
C. Pacha,U. Auer,C. Burwick,Peter Glösekötter,A. Brennemann,Werner Prost,Franz-Josef Tegude,Karl Goser +7 more
TL;DR: The design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated and a novel pipelined carry lookahead addition scheme for this logic family is proposed to improve the speed.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.