Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Dissertation
Méthodes probabilistes d'analyse de fiabilité dans la logique combinatoire
TL;DR: In this article, the authors present a set of modeles and methodologies which prennent en compte l'effet de la logique combinatoire dans la perte de fiabilite.
Low Latency Prefix Accumulation Driven Compound MAC Unit for Efficient FIR Filter Implementation
TL;DR: Results show that proposed method outpaces both formerly projected MAC designs using multiplication methods for attaining high speed and makes improvements made in terms of reduction in latency and merits in performance by the proposed MAC unit are showed through the synthesis done by FPGA hardware.
Patent
Dynamic adder with reduced logic
TL;DR: In this article, a dynamic parallel adder is provided which eliminates the positive (or negative) complimentary carry generate and propagate signal logic normally used to implement a conventional dynamic parallel added, and the method for implementing the incentive adder users a novel XOR configuration constructed with dynamic CMOS logic circuits.
Design of High Speed Based On Parallel Prefix Adders Using In FPGA
TL;DR: This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse KoggesStone, and spanning tree adder) and compares them to the simple Ripple Carry Adder (RCA), finding the carry- tree adders have a speed advantage over the RCA as bit widths approach 256.
Dissertation
Design of efficient VLSI arithmetic circuits
TL;DR: The development of an efficient adder architecture that addresses the problems for higher bit operand lengths like fan-out, wiring complexity, etc is developed and a design for binary INC/DECs is presented that is efficient in terms of speed without compromising on power.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.