Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings ArticleDOI
A multiplier and squarer generator for high performance DSP applications
TL;DR: A generator for multiplier and squarer structures, suitable for high performance bit-parallel DSP applications in VLSI, is presented and shows a delay reduction of 10-20% compared to traditional designs for high speed, as well as a reduction in power and area for a standard 0.8 /spl mu/ CMOS process.
Book ChapterDOI
Systolic Algorithms for Running Order Statistics in Signal and Image Processing
TL;DR: The running order statistics (ROS) problem is defined, a generalization of median smoothing, and algorithms designed for VLSI implementation are presented which solve the ROS problem and are efficient with respect to hardware resources, computation time, and communication bandwidth.
Journal ArticleDOI
Self-timed carry-lookahead adders
TL;DR: In this article, the authors proposed a self-timed carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the log of n. This adder has the best area-time efficiency which is /spl Theta/(nloglogn).
Journal ArticleDOI
Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa
TL;DR: VLSI networks for converting integers from binary to residue number systems are presented and are improvements, with respect to area or time or both of previously proposed solutions.
Proceedings ArticleDOI
A comparison of three rounding algorithms for IEEE floating-point multiplication
Guy Even,P.-M. Seidel +1 more
TL;DR: It is concluded that the new rounding algorithm is the fastest rounding algorithm, provided that an injection can be added in during the reduction of the partial products into a carry-save encoded digit string.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.