Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Book
Three-Dimensional Integrated Circuit Design
TL;DR: In this article, the first book on 3D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.
DissertationDOI
Binary adder architectures for cell-based VLSI and their synthesis
TL;DR: It is found that the ripple-carry, the carry-lookahead, and the proposed carry-increment adders show the best overall performance characteristics for cell-based design.
Journal ArticleDOI
A reduced-area scheme for carry-select adders
TL;DR: The author introduces a scheme to generate carry bits with block-carry-in 1 from the carries of a block withBlock- Carry-in 0 to derive a more area-efficient implementation for both the carry-select and parallel-prefix adders.
Journal ArticleDOI
Area-time-power tradeoffs in parallel adders
TL;DR: A uniform static CMOS layout methodology whereby short circuit power mininization is used as the optimization criterion is adopted and a large adder design space is formulated from which an architect can choose an adder with the desired characteristics.
Journal ArticleDOI
The Area-Time Complexity of Binary Multiplication
TL;DR: By using a model of computation which is a realistic approx~mauon to current and anucipated LSI or VLSI technology, it is shown that A T 2.0 is shown to be the time required to perform multtphcaUon of n-bit binary numbers on a chip.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.