Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings ArticleDOI
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Swaroop Ghosh,Kaushik Roy +1 more
TL;DR: In this article, the authors explore various arithmetic units for possible use in high speed, high yield ALU design at scaled supply voltage with variable latency operation, and demonstrate that careful logic optimization of the existing arithmetic units indeed make them further suitable for supply voltage scaling with tolerable area overhead.
Efficient Interconnection Schemes for VLSI and Parallel Computation
TL;DR: This thesis shows that networks based on Leiserson's fat- tree architecture are nearly as good as any network built in a comparable amount of physical space.
Proceedings ArticleDOI
PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning
Rajarshi Roy,Jonathan Raiman,Neel Kant,Ilyas Elkin,Robert M. Kirby,Michael Siu,Stuart F. Oberman,Saad Godil,Bryan Catanzaro +8 more
TL;DR: In this paper, a grid-based state-action representation and an RL environment for constructing legal prefix circuits are designed and RL agents trained on this environment produce prefix adder circuits that Pareto-dominate existing baselines with up to 16.0% and 30.2% lower area.
Proceedings ArticleDOI
Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI circuit designs
TL;DR: In the proposed structure, the final addition stage of partial products is performed by parallel prefix adders (PPAs), and five Wallace tree multiplier structures are proposed using Kogge stoneAdder, Sklansky adder, Brent Kung adder and Ladner Fischer adder.
Proceedings ArticleDOI
Constant addition utilizing flagged prefix structures
James E. Stine,C.R. Babb,V. Dave +2 more
TL;DR: The paper presents an extension to flagged prefix addition to allow an arbitrary number to be added to the logic to allow difference operations to occur as well.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.