Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings Article
Brent-Kung fast adder dscription, simulation and formal verification using lava
TL;DR: Using Lava a HDL embedded in Haskell, it is explained how to design, simulate, and formal verify a carry chain binary adder and a fast adder parameterized in the size of its inputs.
Journal ArticleDOI
A modified prefix operator well suited for area-efficient brick-based adder implementations
Ingo Rust,Tobias G. Noll +1 more
TL;DR: A modified prefix operator for prefix adders is proposed which is well suited for brick-style layout implementation and, in addition, offers an increase in efficiency.
Efficient Method for Area-Efficient 32bit CSLA
TL;DR: The main focus in this work is to improve the speed of the 32-bit processor and in this case the carry select adder is the better choice.
Journal ArticleDOI
Residue Number Systems — A Tutorial Review
TL;DR: This tutorial review brings together the vast information available and highlights the recent trends to facilitate realization of Fast implementations of DSP algorithms as well as cryptographic processors.
A time driven adder generator architecture
TL;DR: In this article, the authors present a time driven adder generator architecture that allows the parametrization of the architecture to fit ones design constraints, from the word length and the wanted delay the generator outputs a suitable architecture.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.