Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
A fast radix-4 division algorithm and its architecture
H.R. Srinivas,Keshab K. Parhi +1 more
TL;DR: The architecture presented for the proposed algorithm is faster than previously proposed radix-4 dividers, which require at least four digits of the partial remainder to be observed to determine quotient digits.
Journal ArticleDOI
A VLSI modulo m multiplier
G. Alia,E. Martinelli +1 more
TL;DR: The modular multiplier has been evaluated asymptotically, according to the VLSI complexity theory, and it turned out to be an optimal design.
On the Design of Fast IEEE Floating-point Adders (Extended Abstract)
TL;DR: The IEEE floating-point adder (FP-adder) as mentioned in this paper achieves a low latency by combining various optimization techniques such as a non-standard separation into two paths, a simple rounding algorithm, unifying rounding cases for addition and subtraction, sign-magnitude computation of a difference based on one's complement subtraction and compound adders.
Proceedings ArticleDOI
Optimized synthesis of sum-of-products
R. Zimmermann,D.Q. Tran +1 more
TL;DR: In this latest approach to datapath synthesis from RTL, datapaths are extracted into largest possible sum-of-product (SOP) blocks, thus making extensive use of carry-save intermediate results and reducing the number of expensive carry-propagations to a minimum.
Proceedings ArticleDOI
Hybrid Han-Carlson adder
TL;DR: With the new design, the Hybrid Han-Carlson adder, the delay increases slightly, but the complexity, silicon area and power are reduced significantly.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.