Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
Implementation of 32-Bit Carry Select Adder using Brent-Kung Adder
TL;DR: This paper focuses on operation of Parallel Prefix Adders of 32 bit Brent-Kung Adder and the techniques used to get a less amount of delay and area is by using the Binary-to-Excess-1 Converter and a parallel Prefix Adder.
Proceedings ArticleDOI
Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders
TL;DR: Post layout simulations revealed that the optimal sparse carry tree adders provide up to 50% and 22% improvement in energy at same performance over full carry tree Kogge-Stone and Ladner-Fischer adder designs, respectively.
Proceedings ArticleDOI
Area-time optimal adder with relative placement generator
TL;DR: A unique feature of the proposed generator is its integrated synthesis and layout environment achieved by providing relative placement information to the synthesis tool by way of a judicious selection of ripple carry or carry select adders based on computation of delays.
ReportDOI
Adding Faster with Application Specific Early Termination
TL;DR: A methodology for improving the speed of high-speed adders that is able to adapt dynamically to application-specific and adder-specific behavior, resulting in a higher detection rate of fast additions and, consequently, a faster average-case speed for addition.
Journal ArticleDOI
Improved 32-bit conditional sum adder for low-power high-speed applications
Kuo-Hsing Cheng,Shun Wen Cheng +1 more
TL;DR: This 32-bit adder focuses on reducing the numbers of internal nodes and logical gates, while maintaining high speed, and is attractive for use in low-power arithmetic systems.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.