Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings ArticleDOI
Design of High-Speed and Energy-Efficient Parallel Prefix Kogge Stone Adder
U Penchalaiah,Siva Kumar Vg +1 more
TL;DR: A faster and efficient Parallel Prefix Adder (PPA) is introduced, which is developed from the carry look ahead adders, namely Kogge Stone adder (KSA) for 8, 16, 32 and 64-bit addition.
Proceedings ArticleDOI
Binary canonic signed digit multiplier for high-speed digital signal processing
D. Lo lacono,M. Ronchi +1 more
TL;DR: This paper presents a novel high-speed binary CSD (BCSD) multiplier which takes advantage of the benefits coming from the canonic signed digit (CSD) number system, while overcoming the inherent overhead due to the CSD ternary representation.
Proceedings ArticleDOI
Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits
K. Nehru,A. Shanmugam,S. Vadivel +2 more
TL;DR: The proposed 64-bit parallel prefix adder is designed using four different types prefix cell operators, even-dot cells, odd- dot cells and even-semi- Dot cells; it offers robust adder solutions typically used for low power and high-performance design application needs.
Patent
Prefix tree adder with efficient sum generation
TL;DR: In this article, the sum computation logic circuitry is configured to exploit differences in delay associated with generation of the group-generate, group-transmit and intermediate carry signals, so as to reduce the total computational delay of the adder.
A Bibliography of IEEE Transactions on Computers (1980{1989)
TL;DR: (2m± 1) [HGS83b].
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.