Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings ArticleDOI
Design of IIR Filter Using Wallace Tree Multiplier
Karishma Malviya,Ashutosh Nandi +1 more
TL;DR: Based on the simulation results, IIR filter design using Wallace tree multiplier turns out to be more efficient in terms of the speed performance as compared to other IIR Filter design methods.
Journal ArticleDOI
Prototyping design of a flexible DSP block with pipeline structure for FPGA
Hanyang Xu,Jian Wang,Jinmei Lai +2 more
TL;DR: A novel DSP architecture is proposed that can additionally supports multi-operand addition which current commercial devices do not support and is fabricated in 1P10M 65 nm bulk CMOS process.
Journal ArticleDOI
Load balancing in a hybrid ATPG environment
TL;DR: A rule for switching from probabilistic to deterministic test pattern computation is derived based on a model of monitoring of the simulation process and an online estimation of the fault detection probabilities to decide whether it is more efficient to continue fault simulation or to proceed with algorithmic test patterns computation.
Dissertation
Acceleration of a bioinformatics application using high-level synthesis
TL;DR: This research work demonstrates designing flexible hardware accelerators for bioinformatics applications, using design methodologies which are more efficient than the traditional ones, and where resulting designs are scalable enough to meet the future requirements.
Journal ArticleDOI
A systematic design of novel energy efficient 64-bit parallel-prefix adder
Jagadeeshkumar N,D. Meganathan +1 more
TL;DR: The binary addition is the basic operation in digital units like microprocessors, digital systems, and the design of basic functional units in digital systems needs to be revamp.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.