Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings ArticleDOI
Dynamic CMOS circuit techniques for delay and power reduction in parallel adders
H. Lindkvist,P. Andersson +1 more
TL;DR: Simulations indicate that 11-25% decrease of delay at the same time as a 19-29% reduction of power consumption is made possible by combining MCCs with CDPD gates instead of using trees consisting solely of either Mccs of CD PD gates.
Proceedings ArticleDOI
A standard cell automated layout for a CMOS 50 MHz 8*8 bit pipelined parallel Dadda multiplier
TL;DR: An 8*8 bit pipelined parallel multiplier which uses the Dadda scheme is presented, illustrating a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.
Proceedings ArticleDOI
Partitioning and characterization of high speed adder structures in deep-submicron technologies
TL;DR: This communication presents the optimization of adder structures for implementations in deep-submicron technologies through their partitioning into blocks, and allows the characterization of structures implemented inDeep-sub micron technologies for area, delay and power consumption parameters.
Journal ArticleDOI
An integrated co-processor architecture for a smartcard
TL;DR: A prototype VLSI design for a new smartcard co-processor for fast modular arithmetic with long integers is described, and emphasis is put on the manifold constraints which are faced when designing silicon for a smartcard, and on the optimization of algorithms.
Review of carry select adder by using brent kung adder
TL;DR: In this paper, carry select adder (CSLA) is used in many computer data-processing processors to perform fast arithmetic functions to reduce the area and power consumption of the adder.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.