Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Computer Architecture, Fifth Edition: A Quantitative Approach
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High-performance CMOS variability in the 65-nm regime and beyond
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References
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Proceedings ArticleDOI
Area-time complexity for VLSI
TL;DR: The complexity of the Discrete Fourier Transform is studied with respect to a new model of computation appropriate to VLSI technology, which focuses on two key parameters, the amount of silicon area and time required to implement a DFT on a single chip.
Book
Area-Efficient VLSI Computation
TL;DR: The two parts of this thesis address the contribution of communication to the performance and area of an integrated circuit, and provide mathematical views of an engineering discipline: techniques of theoretical computer science--e.g., divide and conquer, automata theory, asymptotic analysis--applied to integrated circuit computation.
Journal ArticleDOI
The Area-Time Complexity of Binary Multiplication
TL;DR: By using a model of computation which is a realistic approx~mauon to current and anucipated LSI or VLSI technology, it is shown that A T 2.0 is shown to be the time required to perform multtphcaUon of n-bit binary numbers on a chip.
Proceedings ArticleDOI
The chip complexity of binary arithmetic
TL;DR: Lower and upper bounds on the area-time complexity for chips that implement binary arithmetic are derived, assuming a model of computation which is intended to approximate, current and anticipated LSI or VLSI technology.