Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library
TL;DR: A novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA) is addressed, using Ling's algorithm to optimise the pre-processing blocks and intermediate Generate-Propagate blocks of the prefix tree to minimise the congestion of wires.
Book ChapterDOI
Architecture of Datapath Circuits
TL;DR: This chapter presents pipelined implementations of arithmetic datapath circuits, which when combined with their constrained and careful placement on the fabric logic, significantly improve their performance.
Journal ArticleDOI
Area Efficient Diminished 2n-1 Modulo Adder using Parallel Prefix Adder
TL;DR: The proposed PPA design using modified carry computation algorithm and reported design used diminished-1 modulo 2n+1 adder structure is presented, which shows a 24.5% saving in area-delay-product (ADP).
Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder
TL;DR: A new approach for high speed and low power multiplier design with less number of gate counts is proposed in the Ripple Counter-based multiplier design, where the number of computational clock cycles is reduced to n for n * n multiplication, which was 2n in the conventional CSAS multiplier.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.