Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Patent
Digital adder circuit
TL;DR: A binary adder circuit includes carry evaluation circuits that encode a carry production control signal using two signal values (V, W) such that V = W = 0 indicates a carry kill, W = 1 indicating a carry generate and V =/W indicates a propagate as mentioned in this paper.
Proceedings ArticleDOI
Variable latency speculative Han-Carlson adders topologies
TL;DR: Synthesis results show that proposed variable latency topologies outperform previously developed speculative Kogge-Stone adders and non-speculative ones, when high-speed is required and that non- Speculative adders remain the best choice when the speed constraint is relaxed.
Journal ArticleDOI
Design issues of arithmetic structures in adiabatic logic
TL;DR: In this article, a comparison of adder structures is performed, based on these results, multipliers and complex systems can be built, and a Discrete Cosine Transformation (DCT) is taken as example for an arithmetic system.
Book ChapterDOI
Qualitative and Quantitative Analysis of Parallel-Prefix Adders
TL;DR: In this article, a comprehensive, qualitative and quantitative analysis of popular parallel prefix adders for various wordlengths (N = 4, 8, 16 and 32) is presented.
Posted Content
Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach
TL;DR: In this paper, a machine learning-based design space exploration methodology is applied to predict the Pareto frontier of the adders in physical domain, which is infeasible by exhaustively running EDA tools on the set of available prefix adder architectures.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.