Showing papers on "Silicon on insulator published in 2016"
TL;DR: The impact active silicon photonic integrated circuits could have on interconnects, telecommunications, sensors, and silicon electronics is reviewed in this article, where the authors present a review of recent breakthroughs in the Silicon photonic technology and components.
Abstract: We review recent breakthroughs in the silicon photonic technology and components, and describe progress in silicon photonic integrated circuits. Heterogeneous silicon photonics has recently demonstrated performance that significantly outperforms native III/V components. The impact active silicon photonic integrated circuits could have on interconnects, telecommunications, sensors, and silicon electronics is reviewed.
265 citations
TL;DR: It is demonstrated that the design method can be expanded to include more modes, in this case including also the second order transverse-electric mode, while maintaining functionality.
Abstract: We design and experimentally verify a topology optimized low-loss and broadband two-mode (de-)multiplexer, which is (de-)multiplexing the fundamental and the first-order transverse-electric modes in a silicon photonic wire. The device has a footprint of 2.6 µm x 4.22 µm and exhibits a loss 14 dB in the C-band. Furthermore, we demonstrate that the design method can be expanded to include more modes, in this case including also the second order transverse-electric mode, while maintaining functionality.
190 citations
TL;DR: In this article, the concepts of silicon-organic hybrid (SOH) and plasmonicorganic hybrid integration (POMHI) integration were proposed, which combine SOI waveguides and PLASmonic nanostructures with organic electro-optic cladding materials.
Abstract: Silicon photonics offers tremendous potential for inexpensive high-yield photonic-electronic integration. Besides conventional dielectric waveguides, plasmonic structures can also be efficiently realized on the silicon photonic platform, reducing device footprint by more than an order of magnitude. However, neither silicon nor metals exhibit appreciable second-order optical nonlinearities, thereby making efficient electro-optic modulators challenging to realize. These deficiencies can be overcome by the concepts of silicon-organic hybrid (SOH) and plasmonic-organic hybrid integration, which combine SOI waveguides and plasmonic nanostructures with organic electro-optic cladding materials.
118 citations
20 Mar 2016
TL;DR: The relative benefits of Silicon nitride and silicon photonics are discussed, which provide an alternative moderate-index-contrast system that is manufacturable in the same CMOS environment.
Abstract: Silicon photonics typically builds on a silicon-on-insulator based high-index-contrast waveguide system. Silicon nitride provides an alternative moderate-index-contrast system that is manufacturable in the same CMOS environment. This paper discusses the relative benefits of both platforms.
111 citations
TL;DR: The first 1.3 μm room-temperature continuous-wave InAs quantum-dot micro-disk lasers epitaxially grown on industrial-compatible Si (001) substrates without offcut are reported, representing a major advancement toward the commercial success of fully integrated silicon photonics.
Abstract: Direct integration of high-performance laser diodes on silicon will dramatically transform the world of photonics, expediting the progress toward low-cost and compact photonic integrated circuits (PICs) on the mainstream silicon platform. Here, we report, to the best of our knowledge, the first 1.3 μm room-temperature continuous-wave InAs quantum-dot micro-disk lasers epitaxially grown on industrial-compatible Si (001) substrates without offcut. The lasing threshold is as low as hundreds of microwatts, similar to the thresholds of identical lasers grown on a GaAs substrate. The heteroepitaxial structure employed here does not require the use of an absorptive germanium buffer and/or dislocation filter layers, both of which impede the efficient coupling of light from the laser active regions to silicon waveguides. This allows for full compatibility with the extensive silicon-on-insulator (SOI) technology. The large-area virtual GaAs (on Si) substrates can be directly adopted in various mature in-plane laser configurations, both optically and electrically. Thus, this demonstration represents a major advancement toward the commercial success of fully integrated silicon photonics.
106 citations
TL;DR: In this paper, the integration strategy of electronic and photonic ICs, 300mm process flow, and process variability are discussed, and performances of the passive and active optical devices are shown.
Abstract: Industrial implementation of a silicon photonics platform using 300-mm SOI wafers and aiming at 100 Gb/s aggregate data-rate application is demonstrated. The integration strategy of electronic and photonic ICs, 300-mm process flow, and process variability are discussed, and performances of the passive and active optical devices are shown. An example of a low-cost LGA-based package together with a fiber assembly is given. RX and TX circuits operating at 25 Gb/s are demonstrated. Finally, the process evolution toward the integration of the backside reflector and multiple silicon etching level is demonstrated.
102 citations
TL;DR: The demonstrated results show that the silicon nanowire has excellent properties for detection of DENV with outstanding repeatability and reproducibility performances.
102 citations
TL;DR: This work presents the first III-V opto-electronic components transfer printed on and coupled to a silicon photonic integrated circuit, comparable to devices realized using a traditional die-to-wafer bonding method.
Abstract: We present the first III-V opto-electronic components transfer printed on and coupled to a silicon photonic integrated circuit. Thin InP-based membranes are transferred to an SOI waveguide circuit, after which a single-spatial-mode broadband light source is fabricated. The process flow to create transfer print-ready coupons is discussed. Aqueous FeCl3 at 5°C was found to be the best release agent in combination with the photoresist anchoring structures that were used. A thin DVS-BCB layer provides a strong bond, accommodating the post-processing of the membranes. The resulting optically pumped LED has a 3 dB bandwidth of 130 nm, comparable to devices realized using a traditional die-to-wafer bonding method.
81 citations
11 Feb 2016-Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment
TL;DR: An overview of the development of semiconductor microdosimetry and the most current (state-of-the-art) Silicon on Insulator (SOI) detectors for micro dosimetry based mainly on research and development carried out at the Centre for Medical Radiation Physics (CMRP) at the University of Wollongong with collaborators over the last 18 years is presented in this article.
Abstract: This paper presents an overview of the development of semiconductor microdosimetry and the most current (state-of-the-art) Silicon on Insulator (SOI) detectors for microdosimetry based mainly on research and development carried out at the Centre for Medical Radiation Physics (CMRP) at the University of Wollongong with collaborators over the last 18 years In this paper every generation of CMRP SOI microdosimeters, including their fabrication, design, and electrical and charge collection characterisation are presented A study of SOI microdosimeters in various radiation fields has demonstrated that under appropriate geometrical scaling, the response of SOI detectors with the well-known geometry of microscopically sensitive volumes will record the energy deposition spectra representative of tissue cells of an equivalent shape This development of SOI detectors for microdosimetry with increased complexity has improved the definition of microscopic sensitive volume (SV), which is modelling the deposition of ionising energy in a biological cell, that are led from planar to 3D SOI detectors with an array of segmented microscopic 3D SVs The monolithic ΔE−E silicon telescope, which is an alternative to the SOI silicon microdosimeter, is presented, and as an example, applications of SOI detectors and ΔE−E monolithic telescope for microdosimetery in proton therapy field and equivalent neutron dose measurements out of field are also presented An SOI microdosimeter “bridge” with 3D SVs can derive the relative biological effectiveness (RBE) in 12C ion radiation therapy that matches the tissue equivalent proportional counter (TEPC) quite well, but with outstanding spatial resolution The use of SOI technology in experimental microdosimetry offers simplicity (no gas system or HV supply), high spatial resolution, low cost, high count rates, and the possibility of integrating the system onto a single device with other types of detectors
74 citations
TL;DR: In this paper, a double-gate structure was proposed to overcome the large mismatch between the ferroelectric and MOS capacitor to enhance the NC effect and reduce the optimized thickness.
Abstract: In this paper, we propose and investigate the high-performance and low-power design space of nonhysteretic negative capacitance (NC) MOSFETs for the 14-nm node based on the calibrated simulations using an experimental gate-stack with PZT ferroelectric to obtain the NC effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to ensure realistic simulation results. The ferroelectric thickness obtained by the proposed approach leads to the maximum enhancement in the nonhysteretic operation of NC transistors. We report a clear and significant double improvement in: 1) subthreshold swing and 2) gate overdrive, using the NC effect. Simulations using Silvaco TCAD coupled with a realistic Landau model of ferroelectrics demonstrates that a 14-nm node ultrathin body and box fully depleted silicon-on-insulator FET can operate at 0.26 V instead of 0.9 V gate voltage using the NC effect, with an average subthreshold swing of 55 mV/decade at room temperature. The double-gate structure is proposed to overcome the large mismatch between the ferroelectric and MOS capacitor to enhance the NC effect and reduce the ferroelectric’s optimized thickness. A 14-nm node double-gate negative capacitance FET can operate at 0.24 V gate voltage with an average subthreshold swing of 45 mV/decade.
74 citations
TL;DR: It is shown for the first time the monolithic integration of InGaAs nanowires on the SOI platform and its feasibility for photonics and optoelectronic applications and the emission from an optically pumped single nanowire is effectively coupled and transmitted through an SOI waveguide.
Abstract: Monolithically integrated III–V semiconductors on a silicon-on-insulator (SOI) platform can be used as a building block for energy-efficient on-chip optical links. Epitaxial growth of III–V semiconductors on silicon, however, has been challenged by the large mismatches in lattice constants and thermal expansion coefficients between epitaxial layers and silicon substrates. Here, we demonstrate for the first time the monolithic integration of InGaAs nanowires on the SOI platform and its feasibility for photonics and optoelectronic applications. InGaAs nanowires are grown not only on a planar SOI layer but also on a 3D structured SOI layer by catalyst-free metal–organic chemical vapor deposition. The precise positioning of nanowires on 3D structures, including waveguides and gratings, reveals the versatility and practicality of the proposed platform. Photoluminescence measurements exhibit that the composition of ternary InGaAs nanowires grown on the SOI layer has wide tunability covering all telecommunicatio...
TL;DR: Electric field intensity enhancements of up to 167 ± 26 for a 24 nm gap are shown, proving the viability of low loss adiabatic nanofocusing on a commercially relevant photonics platform.
Abstract: We present an experimental demonstration of a new class of hybrid gap plasmon waveguides on the silicon-on-insulator (SOI) platform. Created by the hybridization of the plasmonic mode of a gap in a thin metal sheet and the transverse-electric (TE) photonic mode of an SOI slab, this waveguide is designed for efficient adiabatic nanofocusing simply by varying the gap width. For gap widths greater than 100 nm, the mode is primarily photonic in character and propagation lengths can be many tens of micrometers. For gap widths below 100 nm, the mode becomes plasmonic in character with field confinement predominantly within the gap region and with propagation lengths of a few microns. We estimate the electric field intensity enhancement in hybrid gap plasmon waveguide tapers at 1550 nm by three-photon absorption of selectively deposited CdSe/ZnS quantum dots within the gap. Here, we show electric field intensity enhancements of up to 167 ± 26 for a 24 nm gap, proving the viability of low loss adiabatic nanofocus...
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IBM1
TL;DR: In this article, a bilayer buried insulator over a substrate, forming an extremely thin silicon-on-insulator (ETSOI) over the bilayer, forming a dummy gate, and forming a source/drain next to the dummy gate.
Abstract: A method is presented for forming a semiconductor structure. The method includes forming a bilayer buried insulator over a substrate, forming an extremely thin silicon-on-insulator (ETSOI) over the bilayer buried insulator, forming a dummy gate, and forming a source/drain next to the dummy gate, the source/drain defining a raised source/drain region. The method further includes depositing a dielectric material over the raised source/drain regions, removing the dummy gate to define a recess, implanting a species within a first layer of the bilayer buried insulator, and depositing a gate dielectric and a conducting material within the recess. The method further includes removing the substrate, etching the implanted portion of the first layer of the bilayer buried insulator to expose a surface of a second layer of the bilayer buried insulator, and forming a back gate over the exposed second layer, the back gate self-aligned to the ETSOI channel.
14 Jun 2016
TL;DR: In this article, a full 3D CMOS over CMOS CoolCube integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain.
Abstract: For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.
TL;DR: In this paper, the authors investigate the possibility of tuning the spin-orbit interaction (SOI) by electrostatic fields generated by a back gate and two side gates placed on the opposite sides of the indium arsenide nanowires (NWs).
Abstract: Indium arsenide nanowires (NWs) are a promising platform to fabricate quantum electronic devices, among other advantages they have strong spin-orbit interaction (SOI). The controlled tuning of the SOI is desired in spin-based quantum devices. In this study we investigate the possibility of tuning the SOI by electrostatic fields generated by a back gate and two side gates placed on the opposite sides of the NW. The strength of the SOI is analyzed by weak anti-localization effect. We demonstrate that the strength of the SOI can be strongly tuned up to a factor of 2 with the electric field across the NW, while the average electron density is kept constant. Furthermore, a simple electrostatic model is introduced to calculate the expected change of the SOI. Good agreement is found between the experimental results and the estimated Rashba-type SOI generated by the gate-induced electric field.
TL;DR: In this article, the authors have reported design and analysis of polarization independent all optical logic gates in silicon-on-insulator photonic crystal consisting of two dimensional honeycomb lattices with two different air holes exhibiting photonic band gap for both TE and TM mode in the optical communication window.
01 Aug 2016
TL;DR: In this paper, slot waveguides on glass with telecom optical frequencies and strong radiation pressure forces resulting in Brillouin gains on the order of 500 and 50'000 W−1m−1 for backward and forward scattering, respectively.
Abstract: We numerically study silicon waveguides on silica showing that it is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI) material system. Thin waveguides, or fins, exhibit geometrically softened mechanical modes at gigahertz frequencies with phase velocities below the Rayleigh velocity in glass, eliminating acoustic radiation losses. We propose slot waveguides on glass with telecom optical frequencies and strong radiation pressure forces resulting in Brillouin gains on the order of 500 and 50 000 W−1m−1 for backward and forward Brillouin scattering, respectively.
TL;DR: A class of infrared lasers that can be fabricated on the silicon-on-insulator (SOI) integration platform and combine nanophotonic SOI waveguides with dye-doped organic cladding materials that provide optical gain are demonstrated.
Abstract: Silicon photonics enables large-scale photonic-electronic integration by leveraging highly developed fabrication processes from the microelectronics industry. However, while a rich portfolio of devices has already been demonstrated on the silicon platform, on-chip light sources still remain a key challenge since the indirect bandgap of the material inhibits efficient photon emission and thus impedes lasing. Here we demonstrate a class of infrared lasers that can be fabricated on the silicon-on-insulator (SOI) integration platform. The lasers are based on the silicon-organic hybrid (SOH) integration concept and combine nanophotonic SOI waveguides with dye-doped organic cladding materials that provide optical gain. We demonstrate pulsed room-temperature lasing with on-chip peak output powers of up to 1.1 W at a wavelength of 1,310 nm. The SOH approach enables efficient mass-production of silicon photonic light sources emitting in the near infrared and offers the possibility of tuning the emission wavelength over a wide range by proper choice of dye materials and resonator geometry.
TL;DR: In this article, a two dimensional (2D) hetero-dielectric stack gate SOI tunneling field effect transistor (SOI-TFET) with back-gate is proposed.
TL;DR: The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements and the defect-less p + -n source junction formation with steep impurity profiles is a key for high performance TFET operation.
Abstract: CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeO x interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p + -n source junction formation with steep impurity profiles is a key for high performance TFET operation.
TL;DR: In this paper, the integration of III-V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated.
Abstract: The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.
TL;DR: In this paper, a resonant waveguide photodetector exploits carrier generation in silicon-germanium within a microring which is compatible with high-performance electronics, achieving a 3 dB bandwidth of 5 GHz at −4 V bias with a dark current of less than 20
Abstract: A photodiode with 0.55 ± 0.1 A/W responsivity at a wavelength of 1176.9 nm has been fabricated in a 45 nm microelectronics silicon-on-insulator foundry process. The resonant waveguide photodetector exploits carrier generation in silicon-germanium within a microring which is compatible with high-performance electronics. A 3 dB bandwidth of 5 GHz at −4 V bias is obtained with a dark current of less than 20 pA.
TL;DR: 2.0x µm widely tunable external cavity lasers realized by combining a GaSb gain chip with a silicon photonics waveguide circuit for wavelength selection are demonstrated.
Abstract: 2.0x µm widely tunable external cavity lasers realized by combining a GaSb gain chip with a silicon photonics waveguide circuit for wavelength selection are demonstrated. Wavelength tuning over 58 nm from 2.01 to 2.07 µm is demonstrated. In the silicon photonic integrated circuit, laser feedback is realized by using a silicon Bragg grating and continuous tuning is realized by using two thermally tuned silicon microring resonators (MRRs) and a phase section. The uncooled laser has maximum output power of 7.5 mW and threshold current density of 0.8 kA/cm2. The effect of the coupling gap of the MRRs on tunable laser performance is experimentally assessed. A side mode suppression ratio better than 52 dB over the full tuning range and in the optimum operation point of more than 60 dB is achieved for the laser with weakly coupled MRRs.
TL;DR: In this article, a miniature CMOS-compatible silicon-on-insulator (SOI) photothermal transducer for mid-infrared spectroscopy is demonstrated.
Abstract: Mid-infrared spectroscopic techniques rely on the specific ”fingerprint” absorption lines of molecules in the mid-infrared band to detect the presence and concentration of these molecules. Despite being very sensitive and selective, bulky and expensive equipment such as cooled mid-infrared detectors is required for conventional systems. In this paper, we demonstrate a miniature CMOS-compatible Silicon-on-Insulator (SOI) photothermal transducer for mid-infrared spectroscopy which can potentially be made in high volumes and at a low cost. The optical absorption of an analyte in the mid-infrared wavelength range (3.25–3.6 μm) is thermally transduced to an optical transmission change of a microring resonator through the thermo-optic effect in silicon. The photothermal signal is further enhanced by locally removing the silicon substrate beneath the transducer, hereby increasing the effective thermal isolation by a factor of 40. As a proof-of-concept, the absorption spectrum of a polymer that has been locally p...
TL;DR: The scaled-down silicon nanowire exhibited superior performances in terms of good specificity and high sensitivity, which enables for efficient label-free, direct and higher-accuracy DNA molecules detection and serves as novel biosensor for future biomedical diagnostic applications.
Abstract: A top-down nanofabrication approach is used to develop silicon nanowires from silicon-on-insulator (SOI) wafers and involves direct-write electron beam lithography (EBL), inductively coupled plasma-reactive ion etching (ICP-RIE) and a size reduction process. To achieve nanometer scale size, the crucial factors contributing to the EBL and size reduction processes are highlighted. The resulting silicon nanowires, which are 20 nm in width and 30 nm in height (with a triangular shape) and have a straight structure over the length of 400 μm, are fabricated precisely at the designed location on the device. The device is applied in biomolecule detection based on the changes in drain current (Ids), electrical resistance and conductance of the silicon nanowires upon hybridization to complementary target deoxyribonucleic acid (DNA). In this context, the scaled-down device exhibited superior performances in terms of good specificity and high sensitivity, with a limit of detection (LOD) of 10 fM, enables for efficient label-free, direct and higher-accuracy DNA molecules detection. Thus, this silicon nanowire can be used as an improved transducer and serves as novel biosensor for future biomedical diagnostic applications.
12 Jul 2016
TL;DR: Demonstration of a high-density sensor platform with uniform characteristics such as nanoISFET arrays of silicon (Si) in a routine and refined nanofabrication process may serve as an ideal solution deployable for real assay-based applications.
Abstract: As a prerequisite to the development of real label-free bioassay applications, a high-throughput top–down nanofabrication process is carried out with a combination of nanoimprint lithography, anisotropic wet-etching, and photolithography methods realizing nanoISFET arrays that are then analyzed for identical sensor characteristics. Here, a newly designed array-based sensor chip exhibits 32 high aspect ratio silicon nanowires (SiNWs) laid out in parallel with 8 unit groups that are connected to a very highly doped, Π-shaped common source and individual drain contacts. Intricately designed contact lines exert equal feed-line resistances and capacitances to homogenize the sensor response as well as to minimize parasitic transport effects and to render easy integration of a fluidic layer on top. The scalable nanofabrication process as outlined in this article casts out a total of 2496 nanowires (NWs) on a 4 inch p-type silicon-on-insulator (SOI) wafer, yielding 78 sensor chips based on nanoISFET arrays. The s...
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06 Jun 2016TL;DR: In this paper, an antenna switch module and a method of manufacturing the semiconductor device are described. But the authors do not discuss the design of the antenna switch modules and the fabrication process.
Abstract: Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer.
TL;DR: In this paper, two types of metal insulator field effect transistors (MISFETs) were fabricated from Si microwires through a new manufacturing route involving a combination of printing and microfabrication technologies.
Abstract: This paper presents two types of metal insulator field effect transistors (MISFETs) devices fabricated from Si microwires through a new manufacturing route involving a combination of printing and microfabrication technologies. Si microwires, developed through standard photolithography and etching steps, are transferred from a silicon on insulator wafer onto polyimide using stamp-assisted transfer printing. The MISFETs are then obtained by spray coating the dielectric layer and metal contact layer. Spray coating has been introduced here for the first time for deposition of organic dielectric on transfer printed Si microwires. Two groups of the devices are fabricated, one based on a single Si microwire and the other based on the array of 15 microwires of similar dimensions. The variations in the output response of the two groups of devices has been investigated. The devices based on array of microwires are observed to have less variation in the output response, with lesser standard deviations as compared to MISFETs made from single Si microwires.
TL;DR: In this paper, a low-loss dielectric microstrip line (DML) integrated circuit based on silicon technology is proposed for THz applications, and a coupler and a crossover are designed.
Abstract: A low-loss dielectric microstrip line (DML) integrated circuit based on silicon (Si) technology is proposed for THz applications in this paper. Using the DML, a coupler and a crossover are designed. In the proposed technology, all THz passive components are made of high-resistivity silicon on insulator (SOI) wafer. To fabricate the proposed transmission line and its components, we developed a high-precision fabrication process for the SOI wafer. A non-contact measurement technology is used to test the fabricated samples. The measured loss per wavelength of DML ranges from 0.0082 to 0.042 dB/λ over 750–925 GHz. The measured isolation of the crossover is 25.45 ± 5.54 dB, and the measured coupler factor of the coupler is –13.22 ± 3.23 dB.
TL;DR: In this article, tri-gate heterojunction (HJ) FinFETs with different configuration of gate dielectric and gate material stacks were compared with the conventional Fin-FET.