Showing papers on "Silicon on insulator published in 2008"

Thermal and Kerr nonlinear properties of plasma-deposited silicon nitride/ silicon dioxide waveguides.

Abstract: We introduce and present experimental evaluations of loss and nonlinear optical response in a waveguide and an optical resonator, both implemented with a silicon nitride/ silicon dioxide material platform prepared by plasma-enhanced chemical vapor deposition with dual frequency reactors that significantly reduce the stress and the consequent loss of the devices. We measure a relatively small loss of approximately 4dB/cm in the waveguides. The fabricated ring resonators in add-drop and all-pass arrangements demonstrate quality factors of Q=12,900 and 35,600. The resonators are used to measure both the thermal and ultrafast Kerr nonlinearities. The measured thermal nonlinearity is larger than expected, which is attributed to slower heat dissipation in the plasma-deposited silicon dioxide film. The n2 for silicon nitride that is unknown in the literature is measured, for the first time, as 2.4 x 10(-15)cm(2)/W, which is 10 times larger than that for silicon dioxide.

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

Abstract: An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible Tunnel FET performance

Abstract: We report for the first time experimental investigations on SOI, Si1-xGexOI & GeOI Tunnel FET (TFET). These devices were fabricated using a Fully Depleted SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower IOFF (~30fA/mum) compared to co-processed CMOS. We successfully solve the TFET bipolar parasitic conduction by a novel TFET architecture, the Drift Tunnel FET (DTFET), with improved OFF state control. Concerning the ON current issue, we improve the SOI p (resp. n) TFET ION by a factor 55 (resp. 8) by source-drain profiles optimization (via spacers & extensions). Moreover, we demonstrate for the first time functional TFET & CMOS devices on Si1-xGexOI (x=15-30-100%) co-integrated with the same SOI process flow, enabling TFET ION continuous improvement with Ge content increase: ION x2700 for GeOI (compared to SOI).

The Charge Plasma P-N Diode

Abstract: A simulation study on a new rectifier concept is presented. This device basically consists of two gates with different workfunctions on top of a thin intrinsic or lowly doped silicon body. The workfunctions and layer thicknesses are chosen such that an electron plasma is formed on one side of the silicon body and a hole plasma on the other, i.e., a charge plasma p-n diode is formed in which no doping is required. Simulation results reveal a good rectifying behavior for well-chosen gate workfunctions and device dimensions. This concept could be applied for other semiconductor devices and materials as well in which doping is an issue.

Fabrication of low-loss photonic wires in silicon-on-insulator using hydrogen silsesquioxane electron-beam resist

Abstract: Fully etched photonic wires in silicon-on-insulator have been fabricated and propagation loss values as low as 0.92 plusmn 0.14 dB/cm have been obtained. Hydrogen silsesquioxane (HSQ) was used as an electron beam resist and as a direct mask in the dry-etch processing of the silicon core layer. The dimensional repeatability of the fabrication process was also estimated through measurements of the wavelength selection performance of nominally identical photonic wire Bragg gratings fabricated at intervals over a period of 37 days.

Ultra high quality factor one dimensional photonic crystal/photonic wire micro-cavities in silicon-on-insulator (SOI)

Abstract: We present experimental results on photonic crystal/photonic wire micro-cavity structures that demonstrate further enhancement of the quality-factor (Q-factor)--up to approximately 149,000--in the fibre telecommunications wavelength range. The Q-values and the useful transmission levels achieved are due, in particular, to the combination of both tapering within and outside the micro-cavity, with carefully designed hole diameters and non-periodic hole placement within the tapered section. Our 2D Finite Difference Time Domain (FDTD) simulation approach shows good agreement with the experimental results.

Thin-film piezoelectric-on-silicon resonators for high-frequency reference oscillator applications

Abstract: This paper studies the application of lateral bulk acoustic thin-film piezoelectric-on-substrate (TPoS) resonators in high-frequency reference oscillators Low-motional impedance TPoS resonators are designed and fabricated in 2 classes--high-order and coupled-array Devices of each class are used to assemble reference oscillators and the performance characteristics of the oscillators are measured and discussed Since the motional impedance of these devices is small, the transimpedance amplifier (TIA) in the oscillator loop can be reduced to a single transistor and 3 resistors, a format that is very power-efficient The lowest reported power consumption is ~350 muW for an oscillator operating at ~106 MHz A passive temperature compensation method is also utilized bThis paper studies the application of lateral bulk acoustic thin-film piezoelectric-on-substrate (TPoS) resonators in high-frequency reference oscillators Low-motionalimpedance TPoS resonators are designed and fabricated in 2 classes--high-order and coupled-array Devices of each class are used to assemble reference oscillators and the performance characteristics of the oscillators are measured and discussed Since the motional impedance of these devices is small, the transimpedance amplifier (TIA) in the oscillator loop can be reduced to a single transistor and 3 resistors, a format that is very power-efficient The lowest reported power consumption is ~350 muW for an oscillator operating at ~106 MHz A passive temperature compensation method is also utilized by including the buried oxide layer of the silicon-on-insulator (SOI) substrate in the structural resonant body of the device, and a very small (-24 ppm/degC) temperature coefficient of frequency is obtained for an 82-MHz oscillatory including the buried oxide layer of the silicon-on-insulator (SOI) substrate in the structural resonant body of the device, and a very small (-24 ppm/degC) temperature coefficient of frequency is obtained for an 82-MHz oscillator

Piezoelectric-on-Silicon Lateral Bulk Acoustic Wave Micromechanical Resonators

Abstract: This paper reports on the design, fabrication, and characterization of piezoelectrically-transduced micromechanical single-crystal-silicon resonators operating in their lateral bulk acoustic modes to address the need for high-Q microelectronic-integrable frequency-selective components. A simple electromechanical model for optimizing performance is presented. For verification, resonators were fabricated on 5-mum-thick silicon-on- insulator substrates and use a 0.3-mum zinc oxide film for transduction. A bulk acoustic mode was observed from a 240 mum times 40 mum resonator with a 600-Omega impedance (Q=3400 at P=1 atm) at 90 MHz. A linear resonator absorbed power of -0.5 dBm and an output current of 1.3 mA rms were measured. The same device also exhibited a Q of 12 000 in its fundamental extensional mode at a pressure of 5 torr.

Compact optical temporal differentiator based on silicon microring resonator

Abstract: We propose and experimentally demonstrate a temporal differentiator in optical field based on a silicon microring resonator with a radius of 40 µm. The microring resonator operates near the critical coupling region, and can take the first order derivative of the optical field. It features compact size thus is suitable for integration with silicon-on-insulator (SOI) based optical and electronic devices. The performance of this optical differentiator is tested using signals with typical shapes such as Gaussian, sinusoidal and square-like pulses at data rates of 10 Gb/s and 5 Gb/s.

High efficiency diffractive grating couplers for interfacing a single mode optical fiber with a nanophotonic silicon-on-insulator waveguide circuit

Abstract: High efficiency diffractive grating structures to interface a single mode optical fiber and a nanophotonic integrated circuit fabricated on silicon-on-insulator are presented The diffractive grating structures are designed to be inherently very directional by adding a silicon overlay before grating definition 55% coupling efficiency at a wavelength of 153μm is experimentally demonstrated on devices fabricated using standard complementary metal-oxide semiconductor technology By optimizing the grating parameters, we theoretically show that 80% grating coupling efficiency can be obtained for a uniform grating structure

Nonlinear optical properties of silicon waveguides

Abstract: Recent work on two-photon absorption (TPA), stimulated Raman scattering (SRS) and optical Kerr effect in silicon-on-insulator (SOI) waveguides is reviewed and some potential applications of these optical nonlinearities, including silicon-based autocorrelation detectors, optical amplifiers, high speed optical switches, optical wavelength converters and self-phase modulation (SPM), are highlighted. The importance of free carriers generated by TPA in nonlinear devices is discussed, and a generalized definition of the nonlinear effective length to cater for nonlinear losses is proposed. How carrier lifetime engineering, and in particular the use of helium ion implantation, can enhance the nonlinear effective length for nonlinear devices is also discussed.

Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring

Abstract: In order to achieve high density and high performance package, through silicon vias (TSVs) technology has been desired. Our purpose is the development of silicon interposer which has TSVs and fine multilayer Cu wiring on both side. Since silicon substrate has a quite flat and smooth surface, it can be expected to form fine wiring such as global layer of device. Furthermore, silicon interposer can be expected to show high reliability of bump connection for the reason of the same coefficient of thermal expansion (CTE) with silicon devices. In this paper, elemental technologies such as interconnection of TSV, fabrication of fine wiring, and evaluation of interlayer dielectric are reported. Finally, the application of silicon interposer such as silicon module and inorganic-organic hybrid substrate, are described. As further evolution systems, a substrate with micro channel and substrate less package are proposed.

Tungsten-Based SOI Microhotplates for Smart Gas Sensors

Abstract: This paper is concerned with the design, fabrication, and characterization of novel high-temperature silicon on insulator (SOI) microhotplates employing tungsten resistive heaters. Tungsten has a high operating temperature and good mechanical strength and is used as an interconnect in high temperature SOI-CMOS processes. These devices have been fabricated using a commercial SOI-CMOS process followed by a deep reactive ion etching (DRIE) back-etch step, offering low cost and circuit integration. In this paper, we report on the design of microhotplates with different diameters (560 and 300 mum) together with 3-D electrothermal simulation in ANSYS, electrothermal characterization, and analytical analysis. Results show that these devices can operate at high temperatures (600degC ) well beyond the typical junction temperatures of high temperature SOI ICs (225degC), have ultralow dc power consumption (12 mW at 600degC), fast transient time (as low as 2-ms rise time to 600degC), good thermal stability, and, more importantly, a high reproducibility both within a wafer and from wafer to wafer. We also report initial tests on the long-term stability of the tungsten heaters. We believe that this type of SOI microhotplate could be exploited commercially in fully integrated microcalorimetric or resistive gas sensors.

High RF performance TSV silicon carrier for high frequency application

Abstract: Three dimensional system-in-package (3D SiP) based on silicon carriers or interposer is a fast emerging technology that offers system design flexibility and integration of heterogeneous technologies. One of the key technologies enabler for silicon carrier is through silicon via (TSV). The development of 3D SiP will require the devices with different functionality operating at high frequency to be densely packed on the silicon substrate. However, silicon substrate is usually of low resistivity, when a high frequency signal is transmitted vertically through the substrate via, significant signal attenuation can occur that leads to poor RF performance. In this paper, a coaxial TSV structure in silicon carrier is presented for high frequency applications. The coaxial TSV is able to suppress undesirable substrate loss as well as provide good impedance matching. Electrical modeling of coaxial TSV structure was carried out to obtain the required geometries for impedance matching. Three different types of test vehicles were fabricated; Cu-plug TSV in both low (~10 Omega-cm) and high resistivity (~4000 Omega-cm) silicon substrate, and coaxial TSV in low resistivity silicon substrate. The S-parameters of the via structure of the test vehicles were measured from 100 MHz to 10 GHz. The measured results show that the coaxial TSV structure is able to suppress silicon substrate loss and provide good RF performance compared to Cu-plug TSV structure.

Highly efficient vertical outgassing channels for low-temperature InP-to-silicon direct wafer bonding on the silicon-on-insulator substrate

Abstract: The authors report a highly efficient design for low-temperature, void-free InP-to-silicon direct wafer bonding on a silicon-on-insulator (SOI) substrate. By etching an array of small through holes in the top silicon layer, the generated gas by-products (H2O, H2) from bonding polymerization reactions and thus gaseous hydrocarbon can be absorbed and diffuse in the buried oxide layer, resulting in up to five orders of magnitude interfacial void density reduction (from >50 000 to ≤3 cm−2). The required annealing time is reduced to less than 30 min, a ∼100X improvement compared to the previous outgassing design as well. Comprehensive studies in associated processing details, bonding surface energy, universality, and stability are also presented. Successful 50, 75, and 100 mm InP expitaxial layer transfer to the SOI substrate is also demonstrated, which indicates a total elimination of outgassing issues regardless of the wafer bonding dimension. Several incidental advantages leading to a flexible device design...

A Capacitorless 1T-DRAM on SOI Based on Dynamic Coupling and Double-Gate Operation

Abstract: The scaling requirements of conventional DRAMs lead to the recent developments of capacitorless single-transistor (1T) DRAM in SOI technology. We propose a new concept of 1T-DRAM (named MSDRAM), which is simple to fabricate, program, and read. Its basic mechanism is the metastable dip hysteresis effect, which takes advantage of the dynamic coupling between front and back interfaces in SOI transistors. Systematic measurements and simulations show that MSDRAMs are suitable for low-power applications, as they exhibit negligible off-state current and long retention time even for 50-nm devices.

Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation

Abstract: This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability

Trimming of silicon ring resonator by electron beam induced compaction and strain.

Abstract: Silicon is becoming the preferable platform for future integrated components, mostly due to the mature and reliable fabrication capabilities of electronics industry. Nevertheless, even the most advanced fabrication technologies suffer from non-uniformity on wafer scale and on chip scale, causing variations in the critical dimensions of fabricated components. This is an important issue since photonic circuits, and especially cavities such as ring resonators, are extremely sensitive to these variations. In this paper we present a way to circumvent these problems by trimming using electron beam induced compaction of oxide in silicon on insulator. Volume compaction of the oxide cladding causes both changes in the refractive index and creates strain in the silicon lattice. We demonstrate a resonance wavelength red shift 4.91 nm in a silicon ring resonator.

Manufacturing method of fin-type field effect transistor

Abstract: A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is exposed; forming a sacrificial oxide film by oxidizing a surface of the protrusion including a damage inflicted thereon; and forming a fin having a clean surface by removing the sacrificial oxide film by etching, wherein an etching rate r 1 of the sacrificial oxide film is higher than an etching rate r 2 of the buried oxide layer during the etching.

25ps all-optical switching in oxygen implanted silicon-on-insulator microring resonator

Abstract: We present all-optical switching in oxygen ion implanted silicon microring resonators. Time-dependent signal modulation is achieved by shifting resonance wavelengths of microrings through the plasma dispersion effect via femtosecond photogeneration of electron-hole pairs and subsequent trapping at implantation induced defect states. We observe a switching time of 25 ps at extinction ratio of 9 dB and free carrier lifetime of 15 ps for an implantation dose of 7×1012 cm-2. The influence of implantation dose on the switching speed and additional propagation losses of the silicon waveguide – the latter as a result of implantation induced amorphization – is carefully evaluated and in good agreement with theoretical predictions.

Identification of RF Harmonic Distortion on Si Substrates and its Reduction Using a Trap-Rich Layer

Abstract: Harmonic distortion (HD) is measured arising from coplanar waveguide structures on various substrates at 900 MHz, and significant distortion for silicon substrates is demonstrated for the first time. For an input power of +35 dBm, 2nd harmonic power of -47 dBm and 3rd of -57 dBm are measured for a thru calibration structure on oxidized high-resistivity silicon (HRS) substrates, and 2nd harmonic of -23 and 3rd of -20 dBm for a longer line on a thinner oxide. These levels are high compared to a full cellular transmit switch product specification of -45 and -40 dBm for 2nd and 3rd harmonics, respectively, at similar power levels. The contribution of the silicon substrate to high harmonic levels is investigated experimentally, and an efficient technological solution based on the introduction of a trap-rich layer is demonstrated.

Silicon photonic crystal nanostructures for refractive index sensing

Abstract: The authors present the fabrication and optical investigation of silicon on insulator photonic crystal drop filters for use as refractive index sensors. Two types of defect nanocavities (L3 and H1−r) are embedded between two W1 photonic crystal waveguides to evanescently route light at the cavity mode frequency between input and output waveguides. Optical characterization of the structures in air and various liquids demonstrates detectivities in excess of Δn/n=0.018 and Δn/n=0.006 for the H1−r and L3 cavities, respectively. The measured cavity frequencies and detector refractive index responsivities are in good agreement with simulations, demonstrating that the method provides a background free transducer signal with frequency selective addressing of a specific area of the sensor chip.

Silicon Nanotweezers With Subnanometer Resolution for the Micromanipulation of Biomolecules

Abstract: We describe electrostatically actuated silicon nanotweezers which are intended for the manipulation and characterization of filamentary molecules. The microelectromechanical system consists of a pair of opposing tips whose distance can be accurately adjusted by means of an integrated differential capacitive sensor. The fabrication process is based on silicon-on-insulator technology and combines KOH wet anisotropic etching and deep reactive ion etching of silicon to form sharp nanotips and high aspect ratio microstructures, respectively. In the designed prototype, the initial gap between the tips was around 20 mum. The device showed a maximum displacement of about 2.5 mum, and we could achieve a resolution better than 0.2 nm (in static mode). We measured a resonant frequency of 2.5 kHz and a quality factor (Q factor) of 50 in air. The instrument was used to perform static and dynamic mechanical manipulations on DNA molecules, and we could distinctly observe the viscoelastic behavior of DNA bundles from these experiments.

Photodetection in Silicon Beyond the Band Edge with Surface States

Abstract: Silicon is an extremely attractive material platform for integrated optics at telecommunications wavelengths, particularly for integration with CMOS circuits. Developing detectors and electrically pumped lasers at telecom wavelengths are the two main technological hurdles before silicon can become a comprehensive platform for integrated optics. We report on the generation of free carriers in unimplanted SOI ridge waveguides, which we attribute to surface state absorption. By electrically contacting the waveguides, a photodetector with a responsivity of 36 mA/W and quantum efficiency of 2.8% is demonstrated. The photoconductive effect is shown to have minimal falloff at speeds of up to 60 Mhz.

A capacitive vibration-to-electricity energy converter with integrated mechanical switches

Abstract: Due to recent advances in low-power VLSI design technology, it has become feasible to power portable or remote electronic devices by scavenging the ambient energy. The design, fabrication and measurement of a capacitive vibration-to-electricity energy converter are presented in this paper. With a device area constraint of 1 cm2 and an auxiliary battery supply of 3.6 V, the device was designed to generate an output power of 31 µW with an output saturation voltage of 40 V. An external mass of 4 g was needed to adjust the device resonance to match the input vibration of 2.25 m s−2 at 120 Hz. Mechanical contact switches were integrated onto the device to provide accurate charge–discharge energy conversion timing. The device was fabricated in SOI (silicon-on-insulator) wafers by deep silicon etching technology. Parasitic capacitance was minimized by partial back side substrate removal. Resonant frequencies of the fabricated device with and without the external mass agreed with the expected values. Without the external mass, the measured ac output power was 1.2 µW with a load of 5 MΩ at 1870 Hz. Detailed circuit modeling and ac output power measurement of the devices with the external mass attached are in progress.

A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond

Abstract: A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate (BG) doping, and raised source-drain epitaxy. Retention of a minimum 3-muA sensing window for 100 ms, in devices with 60-nm gate-length (Lg) and 70-nm diffusion width (W), represents the best retention time of all sub-100-nm FBC devices. FBC scaling is predicted to be feasible at least to 40-nm Lg, enabling memory cell sizes much smaller than 6T-SRAM at 16-nm technology node. Functional 32-nm Lg devices suggest the feasibility at the 11-nm technology node.

A 3D micromechanical compass

Abstract: We have designed and fabricated micromechanical magnetometers intended for a 3D electronic compass which could be embedded in portable devices. The sensors are based on the Lorentz force acting on a current-carrying coil, processed on a single crystal silicon resonator, and they are operated in vacuum to reach high enough Q values. Sensors for all cartesian components of the magnetic field vector can be processed on the same chip. The vibration amplitude is detected capacitively and the resonance is tracked by a phase-locked-loop circuit. The fabrication process is based on aligned direct bonding of a double side polished silicon wafer and a SOI wafer. Magnetometers measuring the field component along the chip surface have a flux density resolution of about 10 nT/√Hz at a coil current of 100 μA. Magnetometers measuring the field component perpendicular to the chip surface are currently less sensitive with a flux density resolution of about 70 nT/√Hz. The standard deviation of the signal was less than 1% over a period of a few days.

Method of manufacturing vibrating micromechanical structures

Abstract: A method for fabrication of single crystal silicon micromechanical resonators using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, a capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; viewing windows are opened in the active layer of the resonator wafer; masking the single crystal silicon semiconductor material active layer of the resonator wafer with photoresist material; a single crystal silicon resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist material is subsequently dry stripped.

Cascade wide-angle Y-junction 1 x 16 optical power splitter based on silicon wire waveguides on silicon-on-insulator.

Abstract: A 1 x 16 optical power splitter with wide splitting angle, uniform outputs, and low excess loss is demonstrated. The 1 x 16 splitter comprising cascaded 1 x 2 splitters with arc-shaped branching waveguides is fabricated on the silicon-on-insulator (SOI) substrate. The gap between the branching waveguides is widened in a short propagation length such that influences of etch residues and air voids in the gap on the optical power uniformity are reduced significantly. The measured power uniformity of the 1 x 16 splitter is better than 0.3 dB at wavelength of 1550 nm.