Showing papers on "Field-effect transistor published in 2016"
TL;DR: A field-effect transistor (FET) based on ultrathin Ti3 C2 -MXene micropatterns is developed and utilized as a highly sensitive biosensor and fast detection of action potentials in primary neurons is demonstrated.
Abstract: A field-effect transistor (FET) based on ultrathin Ti3 C2 -MXene micropatterns is developed and utilized as a highly sensitive biosensor. The device is produced with the microcontact printing technique, making use of its unique advantages for easy fabrication. Using the MXene-FET device, label-free probing of small molecules in typical biological environments and fast detection of action potentials in primary neurons is demonstrated.
445 citations
TL;DR: This work reports on single crystal rubrene transistors intentionally fabricated to exhibit an abrupt turn-on, and disentangle the channel properties from the contact resistance by using impedance spectroscopy and shows that the current in such devices is governed by a gate bias dependence of theContact resistance.
Abstract: Parameters used to describe the electrical properties of organic field-effect transistors, such as mobility and threshold voltage, are commonly extracted from measured current-voltage characteristics and interpreted by using the classical metal oxide-semiconductor field-effect transistor model. However, in recent reports of devices with ultra-high mobility (>40 cm(2) V(-1) s(-1)), the device characteristics deviate from this idealized model and show an abrupt turn-on in the drain current when measured as a function of gate voltage. In order to investigate this phenomenon, here we report on single crystal rubrene transistors intentionally fabricated to exhibit an abrupt turn-on. We disentangle the channel properties from the contact resistance by using impedance spectroscopy and show that the current in such devices is governed by a gate bias dependence of the contact resistance. As a result, extracted mobility values from d.c. current-voltage characterization are overestimated by one order of magnitude or more.
411 citations
TL;DR: The experimental results presented in this work, combined with device transport modeling, reveal the remarkable potential of 2D MoS2 for future sub-10 nm technology nodes.
Abstract: Atomically thin molybdenum disulfide (MoS2) is an ideal semiconductor material for field-effect transistors (FETs) with sub-10 nm channel lengths. The high effective mass and large bandgap of MoS2 minimize direct source–drain tunneling, while its atomically thin body maximizes the gate modulation efficiency in ultrashort-channel transistors. However, no experimental study to date has approached the sub-10 nm scale due to the multiple challenges related to nanofabrication at this length scale and the high contact resistance traditionally observed in MoS2 transistors. Here, using the semiconducting-to-metallic phase transition of MoS2, we demonstrate sub-10 nm channel-length transistor fabrication by directed self-assembly patterning of mono- and trilayer MoS2. This is done in a 7.5 nm half-pitch periodic chain of transistors where semiconducting (2H) MoS2 channel regions are seamlessly connected to metallic-phase (1T′) MoS2 access and contact regions. The resulting 7.5 nm channel-length MoS2 FET has a low ...
377 citations
TL;DR: The 2D/2D low-resistance ohmic contacts presented here represent a new device paradigm that overcomes a significant bottleneck in the performance of TMDs and a wide variety of other 2D materials as the channel materials in postsilicon electronics.
Abstract: We report a new strategy for fabricating 2D/2D low-resistance ohmic contacts for a variety of transition metal dichalcogenides (TMDs) using van der Waals assembly of substitutionally doped TMDs as drain/source contacts and TMDs with no intentional doping as channel materials. We demonstrate that few-layer WSe2 field-effect transistors (FETs) with 2D/2D contacts exhibit low contact resistances of ∼0.3 kΩ μm, high on/off ratios up to >10(9), and high drive currents exceeding 320 μA μm(-1). These favorable characteristics are combined with a two-terminal field-effect hole mobility μFE ≈ 2 × 10(2) cm(2) V(-1) s(-1) at room temperature, which increases to >2 × 10(3) cm(2) V(-1) s(-1) at cryogenic temperatures. We observe a similar performance also in MoS2 and MoSe2 FETs with 2D/2D drain and source contacts. The 2D/2D low-resistance ohmic contacts presented here represent a new device paradigm that overcomes a significant bottleneck in the performance of TMDs and a wide variety of other 2D materials as the channel materials in postsilicon electronics.
327 citations
TL;DR: A CMOS compatible, controllable and area selective phosphorus plasma immersion ion implantation (PIII) process for p-type doping of MoS2 is reported, with physical characterization using SIMS, AFM, XRD and Raman techniques used to identify process conditions with reduced lattice defects as well as low surface damage and etching.
Abstract: P-type doping of MoS2 has proved to be a significant bottleneck in the realization of fundamental devices such as p-n junction diodes and p-type transistors due to its intrinsic n-type behavior. We report a CMOS compatible, controllable and area selective phosphorus plasma immersion ion implantation (PIII) process for p-type doping of MoS2. Physical characterization using SIMS, AFM, XRD and Raman techniques was used to identify process conditions with reduced lattice defects as well as low surface damage and etching, 4X lower than previous plasma based doping reports for MoS2. A wide range of nondegenerate to degenerate p-type doping is demonstrated in MoS2 field effect transistors exhibiting dominant hole transport. Nearly ideal and air stable, lateral homogeneous p-n junction diodes with a gate-tunable rectification ratio as high as 2 × 104 are demonstrated using area selective doping. Comparison of XPS data from unimplanted and implanted MoS2 layers shows a shift of 0.67 eV toward lower binding energie...
309 citations
TL;DR: In this paper, a top-down BCl3 plasma etching on a native semi-insulating Mg-doped (100) β-Ga2O3 substrate was used to construct fin-array field effect transistors (finFETs).
Abstract: Sn-doped gallium oxide (Ga2O3) wrap-gate fin-array field-effect transistors (finFETs) were formed by top-down BCl3 plasma etching on a native semi-insulating Mg-doped (100) β-Ga2O3 substrate. The fin channels have a triangular cross-section and are approximately 300 nm wide and 200 nm tall. FinFETs, with 20 nm Al2O3 gate dielectric and ∼2 μm wrap-gate, demonstrate normally-off operation with a threshold voltage between 0 and +1 V during high-voltage operation. The ION/IOFF ratio is greater than 105 and is mainly limited by high on-resistance that can be significantly improved. At VG = 0, a finFET with 21 μm gate-drain spacing achieved a three-terminal breakdown voltage exceeding 600 V without a field-plate.
284 citations
TL;DR: In this article, the authors reported quasi-ballistic CNT array FETs at a density of 47 CNTs μm−1, fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment.
Abstract: Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G0 = 4e2/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm−1, fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm−1, which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm−1 and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies.
259 citations
TL;DR: The scaling of transistors to sub-10 nm dimensions is strongly limited by their contact resistance (Rc), as shown in this article, where the authors present a systematic study of scaling MoS2 devices and contacts with varying electrode metals and controlled deposition conditions.
Abstract: The scaling of transistors to sub-10 nm dimensions is strongly limited by their contact resistance (Rc). Here we present a systematic study of scaling MoS2 devices and contacts with varying electrode metals and controlled deposition conditions, over a wide range of temperatures (80 to 500 K), carrier densities (10^12 to 10^13 1/cm^2), and contact dimensions (20 to 500 nm). We uncover that Au deposited in ultra-high vacuum (~10^-9 Torr) yields three times lower Rc than under normal conditions, reaching 740 {\Omega}.{\mu}m and specific contact resistivity 3x10^-7 {\Omega}.cm2, stable for over four months. Modeling reveals separate Rc contributions from the Schottky barrier and the series access resistance, providing key insights on how to further improve scaling of MoS2 contacts and transistor dimensions. The contact transfer length is ~35 nm at 300 K, which is verified experimentally using devices with 20 nm contacts and 70 nm contact pitch (CP), equivalent to the "14 nm" technology node.
232 citations
TL;DR: In this paper, the authors demonstrate a nearly hysteresis-free sub-60mV/decade subthreshold swing operation in a p-type bulk metaloxide-semiconductor field effect transistor externally connected to a ferroelectric capacitor.
Abstract: We demonstrate a nearly hysteresis-free sub-60-mV/decade subthreshold swing (SS) operation in a p-type bulk metal–oxide–semiconductor field-effect transistor externally connected to a ferroelectric capacitor. The SS $\mu \text{m}\sim 10$ nA/ $\mu \text{m}$ of drain current) and at large drain current levels. However, the extent of hysteresis is found to be strongly dependent on the drain voltage. At high drain voltages, large hysteresis occurs, indicating the influence of drain voltage in the charge balance with the ferroelectric capacitor.
181 citations
TL;DR: In this paper, the carrier type of WSe2 field effect transistors (FETs) is controlled via thickness engineering and solid-state oxide doping, which are compatible with state-of-the-art integrated circuit processing.
Abstract: Control of the carrier type in 2D materials is critical for realizing complementary logic computation. Carrier type control in WSe2 field-effect transistors (FETs) is presented via thickness engineering and solid-state oxide doping, which are compatible with state-of-the-art integrated circuit (IC) processing. It is found that the carrier type of WSe2 FETs evolves with its thickness, namely, p-type ( 15 nm). This layer-dependent carrier type can be understood as a result of drastic change of the band edge of WSe2 as a function of the thickness and their band offsets to the metal contacts. The strong carrier type tuning by solid-state oxide doping is also demonstrated, in which ambipolar characteristics of WSe2 FETs are converted into pure p-type, and the field-effect hole mobility is enhanced by two orders of magnitude. The studies not only provide IC-compatible processing method to control the carrier type in 2D semiconductor, but also enable to build functional devices, such as, a tunable diode formed with an asymmetrical-thick WSe2 flake for fast photodetectors.
173 citations
11 Jul 2016
TL;DR: In this paper, a combined study of both the hysteresis as well as the arguably most important reliability issue, the bias-temperature instability, was performed on single-layer MoS2 FETs with SiO2 and hBN insulators and demonstrated that both phenomena are indeed due to traps in the gate insulator with time constants distributed over wide timescales.
Abstract: The commonly observed hysteresis in the transfer characteristics of MoS2 transistors is typically associated with charge traps in the gate insulator. Since in Si technologies such traps can lead to severe reliability issues, we perform a combined study of both the hysteresis as well as the arguably most important reliability issue, the bias-temperature instability. We use single-layer MoS2 FETs with SiO2 and hBN insulators and demonstrate that both phenomena are indeed due to traps in the gate insulator with time constants distributed over wide timescales, where the faster ones lead to hysteresis and the slower ones to bias-temperature instabilities. Our data show that the use of hBN as a gate insulator considerably reduces the number of accessible slow traps and thus improves the reliability. However, the reliability of hBN insulators deteriorates with increasing temperature due to the thermally activated nature of charge trapping.
TL;DR: Applications of organophosphorus materials range from single molecule sensors, field effect transistors, organic light emitting diodes, to polymeric materials for organic photovoltaic applications.
Abstract: This Minireview describes recent advances of organophosphorus compounds as opto-electronic materials in the field of organic electronics. The progress of (hetero-) phospholes, unsaturated phosphanes, and trivalent and pentavalent phosphanes since 2010 is covered. The described applications of organophosphorus materials range from single molecule sensors, field effect transistors, organic light emitting diodes, to polymeric materials for organic photovoltaic applications.
TL;DR: Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps, so a bottom-up synthesis approach is used to fabricate 9- and 13-atom wide ribbons enabling short-channel transistors with 105 on-off current ratio.
Abstract: Bottom-up synthesized GNRs and GNR heterostructures have promising electronic properties for high performance field effect transistors (FETs) and ultra-low power devices such as tunnelling FETs. However, the short length and wide band gap of these GNRs have prevented the fabrication of devices with the desired performance and switching behaviour. Here, by fabricating short channel (Lch ~20 nm) devices with a thin, high-k gate dielectric and a 9-atom wide (0.95 nm) armchair GNR as the channel material, we demonstrate FETs with high on-current (Ion >1 uA at Vd = -1 V) and high Ion/Ioff ~10^5 at room temperature. We find that the performance of these devices is limited by tunnelling through the Schottky barrier (SB) at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high performance short-channel FETs with bottom-up synthesized armchair GNRs.
TL;DR: In this paper, a 2D channel thin film made from liquid phase exfoliated molybdenum oxide nanoflake inks with highly controllable substoichiometric levels is presented.
Abstract: Planar 2D materials are possibly the ideal channel candidates for future field effect transistors (FETs), due to their unique electronic properties. However, the performance of FETs based on 2D materials is yet to exceed those of conventional silicon based devices. Here, a 2D channel thin film made from liquid phase exfoliated molybdenum oxide nanoflake inks with highly controllable substoichiometric levels is presented. The ability to induce oxygen vacancies by solar light irradiation in an aqueous environment allows the tuning of electronic properties in 2D substoichiometric molybdenum oxides (MoO3−x). The highest mobility is found to be ≈600 cm2 V−1 s−1 with an estimated free electron concentration of ≈1.6 × 1021 cm−3 and an optimal IOn/IOff ratio of >105 for the FETs made of 2D flakes irradiated for 30 min (x = 0.042). These values are significant and represent a real opportunity to realize the next generation of tunable electronic devices using electronic inks.
TL;DR: Inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics are fabricated, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface.
Abstract: We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300 °C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5 μm were 1.6 mA/mm and 8.0 cm2/Vs, respectively, at room temperature.
TL;DR: In this paper, the authors reported on high performance depletion/enhancement (D/E)-mode beta-Ga2O3 on insulator (GOOI) field effect transistors (FETs) with record high drain currents (ID) of 600/450 mA/mm, which are nearly one order of magnitude higher than any other reported ID values.
Abstract: In this letter, we report on high performance depletion/enhancement (D/E)-mode beta-Ga2O3 on insulator (GOOI) field-effect transistors (FETs) with record high drain currents (ID) of 600/450 mA/mm, which are nearly one order of magnitude higher than any other reported ID values. The threshold voltage (VT) can be modulated by varying the thickness of the beta-Ga2O3 films and the E-mode GOOI FET can be simply achieved by shrinking the beta-Ga2O3 film thickness. Benefiting from the good interface between beta-Ga2O3 and SiO2 and wide bandgap of beta-Ga2O3, a negligible transfer characteristic hysteresis, high ID on/off ratio of 10^10, and low subthreshold swing of 140 mV/dec for a 300 nm thick SiO2 are observed. E-mode GOOI FET with source to drain spacing of 0.9 um demonstrates a breakdown voltage of 185 V and an average electric field (E) of 2 MV/cm, showing the great promise of GOOI FET for future power devices.
TL;DR: This work reports for the first time BP nanosheet-ZnO nanowire 2D-1D heterojunction applications for p-n diodes and BP-gated junction field effect transistors (JFETs) with n-ZNO channel on glass and takes advantages of the mechanical flexibility of p-type conducting of BP and van der Waals junction interface between BP and ZnO.
Abstract: Black phosphorus (BP) nanosheet is two-dimensional (2D) semiconductor with distinct band gap and attracting recent attention from researches because it has some similarity to gapless 2D semiconductor graphene in the following two aspects: single element (P) for its composition and quite high mobilities depending on its fabrication conditions. Apart from several electronic applications reported with BP nanosheet, here we report for the first time BP nanosheet–ZnO nanowire 2D–1D heterojunction applications for p–n diodes and BP-gated junction field effect transistors (JFETs) with n-ZnO channel on glass. For these nanodevices, we take advantages of the mechanical flexibility of p-type conducting of BP and van der Waals junction interface between BP and ZnO. As a result, our BP–ZnO nanodimension p–n diode displays a high ON/OFF ratio of ∼104 in static rectification and shows kilohertz dynamic rectification as well while ZnO nanowire channel JFET operations are nicely demonstrated by BP gate switching in both ...
TL;DR: A monolayer chemical-vapour-deposited graphene hydrogenated by indirect hydrogen plasma is shown and it is demonstrated that a band gap can be tuned as wide as 3.9 eV by varying hydrogen coverage and a hydrogenated graphene field-effect transistor is shown, showing that on/off ratio changes over three orders of magnitude at room temperature.
Abstract: Graphene is currently at the forefront of cutting-edge science and technology due to exceptional electronic, optical, mechanical, and thermal properties. However, the absence of a sizeable band gap in graphene has been a major obstacle for application. To open and control a band gap in functionalized graphene, several gapping strategies have been developed. In particular, hydrogen plasma treatment has triggered a great scientific interest, because it has been known to be an efficient way to modify the surface of single-layered graphene and to apply for standard wafer-scale fabrication. Here we show a monolayer chemical-vapour-deposited graphene hydrogenated by indirect hydrogen plasma without structural defect and we demonstrate that a band gap can be tuned as wide as 3.9 eV by varying hydrogen coverage. We also show a hydrogenated graphene field-effect transistor, showing that on/off ratio changes over three orders of magnitude at room temperature.
TL;DR: Exfoliated flakes of MoS2 with various thicknesses were successfully fabricated into field-effect transistors (FETs) to measure the thickness and temperature dependences of electrical mobility, and the promise of few-layer transition metal dichalcogenides as candidates for potential optoelectronic applications is indicated.
Abstract: Molybdenum disulfide (MoS2) is currently under intensive study because of its exceptional optical and electrical properties in few-layer form. However, how charge transport mechanisms vary with the number of layers in MoS2 flakes remains unclear. Here, exfoliated flakes of MoS2 with various thicknesses were successfully fabricated into field-effect transistors (FETs) to measure the thickness and temperature dependences of electrical mobility. For these MoS2 FETs, measurements at both 295 K and 77 K revealed the maximum mobility for layer thicknesses between 5 layers (~3.6 nm) and 10 layers (~7 nm), with ~70 cm2 V−1 s−1 measured for 5 layer devices at 295 K. Temperature-dependent mobility measurements revealed that the mobility rises with increasing temperature to a maximum. This maximum occurs at increasing temperature with increasing layer thickness, possibly due to strong Coulomb scattering from charge impurities or weakened electron–phonon interactions for thicker devices. Temperature-dependent conductivity measurements for different gate voltages revealed a metal-to-insulator transition for devices thinner than 10 layers, which may enable new memory and switching applications. This study advances the understanding of fundamental charge transport mechanisms in few-layer MoS2, and indicates the promise of few-layer transition metal dichalcogenides as candidates for potential optoelectronic applications.
TL;DR: High-temperature/high-voltage operation of quasi-2D β-Ga2O3 nano-belts contrasts with traditional 2D materials such as transition metal dichalcogenides that intrinsically have limited temperature and power operational envelopes owing to their narrow bandgap.
Abstract: This study demonstrated the exfoliation of a two-dimensional (2D) β-Ga2O3 nano-belt and subsequent processing into a thin film transistor structure. This mechanical exfoliation and transfer method produces β-Ga2O3 nano-belts with a pristine surface as well as a continuous defect-free interface with the SiO2/Si substrate. This β-Ga2O3 nano-belt based transistor displayed an on/off ratio that increased from approximately 104 to 107 over the operating temperature range of 20 °C to 250 °C. No electrical breakdown was observed in our measurements up to VDS = +40 V and VGS = −60 V between 25 °C and 250 °C. Additionally, the electrical characteristics were not degraded after a month-long storage in ambient air. The demonstration of high-temperature/high-voltage operation of quasi-2D β-Ga2O3 nano-belts contrasts with traditional 2D materials such as transition metal dichalcogenides that intrinsically have limited temperature and power operational envelopes owing to their narrow bandgap. This work motivates the application of 2D β-Ga2O3 to high power nano-electronic devices for harsh environments such as high temperature chemical sensors and photodetectors as well as the miniaturization of power circuits and cooling systems in nano-electronics.
TL;DR: An accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications and accurately captures different aspects of NCFET is presented.
Abstract: We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau–Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.
TL;DR: In this article, a 2D analytical model for electrical characteristics such as surface potential, drain current, and threshold voltage of double-gate tunnel FETs with a SiO2/High- ${k}$ stacked gate-oxide structure is proposed.
Abstract: A compact 2-D analytical model for electrical characteristics such as surface potential, drain current, and threshold voltage of double-gate tunnel FET (DG TFETs) with a SiO2/High- ${k}$ stacked gate-oxide structure is proposed in this paper. Poisson’s equation has been solved using parabolic approximation method to model the channel potential. The band-to-band tunneling generation rate has been expressed as a function of channel electric field derived from the channel potential and then integrated analytically over the channel thickness to derive the drain current of the stacked-gate DG TFETs using the shortest tunneling path $(L_{t}^{\min } )$ concept. The effect of source/drain depletion regions has been included for the better accuracy of the proposed model. The maximum transconductance method has finally been used to extract the threshold voltage from the drain current of the device. The effects of various device parameters on the channel potential, drain current, and threshold voltage have been investigated. The model results have been compared with the simulation data obtained using the commercially available ATLAS 2-D device simulator from SILVACO for the validity of the proposed model.
TL;DR: In this paper, a 2D tin monoxide (SnO) layer-by-layer growth of SnO on sapphire and SiO2 substrates is demonstrated using a pulsed laser deposition method.
Abstract: 2D materials are considered promising candidates for developing next-generation high-performance energy efficient electronic, optoelectronic, and valley-tronic devices. Though metal oxides are widely used in the fabrication of many advanced devices, very little work has been reported on their properties in 2D limit. This article reports the discovery of a new 2D materials system, 2D tin monoxide (SnO). Layer by layer growth of SnO on sapphire and SiO2 substrates is demonstrated using a pulsed laser deposition method. The number of SnO layers is controlled by controlling the number of laser shots during the deposition process. Raman spectroscopic and X-ray photoelectron spectroscopic analysis confirms the formation of phase pure SnO layers. Field effect transistors (FETs) using few layer SnO channels grown on SiO2 substrates are successfully fabricated. These FETs show typical p-channel conduction with field effect mobility ranging from 0.05 to 1.9 cm2 V−1 s−1. Field effect mobility varies with the number of SnO layers and decreases on either sides of the optimum layer numbers (12), which is explained based on charge screening and interlayer coupling in layered materials.
TL;DR: In this article, the authors showed that controlled heating in air significantly improves device performance of WSe2 FETs in terms of on-state currents and field-effect mobilities.
Abstract: Monolayer WSe2 is a two-dimensional (2D) semiconductor with a direct band gap, and it has been recently explored as a promising material for electronics and optoelectronics. Low field-effect mobility is the main constraint preventing WSe2 from becoming one of the competing channel materials for field-effect transistors (FETs). Recent results have demonstrated that chemical treatments can modify the electrical properties of transition metal dichalcogenides (TMDCs), including MoS2 and WSe2. Here, we report that controlled heating in air significantly improves device performance of WSe2 FETs in terms of on-state currents and field-effect mobilities. Specifically, after being heated at optimized conditions, chemical vapor deposition grown monolayer WSe2 FETs showed an average FET mobility of 31 cm2·V–1·s–1 and on/off current ratios up to 5 × 108. For few-layer WSe2 FETs, after the same treatment applied, we achieved a high mobility up to 92 cm2·V–1·s–1. These values are significantly higher than FETs fabricat...
TL;DR: A single cell of an integrated device and a 2 × 2 electrophysiology array succeed in detecting electromyogram with local stimulation of the motor nerve bundle of a transgenic rat by a laser pulse.
Abstract: A study was conducted to demonstrate the possibility of spatial distribution measurement of myoelectric signals with a 2x2 electrophysiology array. The device was placed on a gracilis muscle covering both light-activated muscle area and non-activated muscle areas. The activation distribution of the muscle was confirmed by measuring the evoked myoelectric potentials using a conventional needle electrode. The result of spatial distribution of the measured myoelectric signals using a 2x2 electrophysiology array complied with results from the needle electrode The organic electrochemical transistors (OECT) was successfully operated by the organic field effect transistors (OFET). The developed integrated circuit with the OECT and the OFET, revealed a fast time response and flexibility in recording the biological signal reliably even on a moving tissue surface. The OECT operated by the OFET the provided the circuit design for a multi-array OECT in an active matrix.
TL;DR: Using electrical characteristics from three-terminal field-effect transistors (FETs), substantial strain induced band gap tunability in transition metal dichalcogenides (TMDs) is demonstrated in line with theoretical predictions and optical experiments.
Abstract: Using electrical characteristics from three-terminal field-effect transistors (FETs), we demonstrate substantial strain induced band gap tunability in transition metal dichalcogenides (TMDs) in line with theoretical predictions and optical experiments. Devices were fabricated on flexible substrates, and a cantilever sample holder was used to apply uniaxial tensile strain to the various multilayer TMD FETs. Analyzing in particular transfer characteristics, we argue that the modified device characteristics under strain are clear evidence of a band gap reduction of 100 meV in WSe2 under 1.35% uniaxial tensile strain at room temperature. Furthermore, the obtained device characteristics imply that the band gap does not shrink uniformly under strain relative to a reference potential defined by the source/drain contacts. Instead, the band gap change is only related to a change of the conduction band edge of WSe2, resulting in a decrease in the Schottky barrier (SB) for electrons without any change for hole injec...
TL;DR: In this paper, double-gate (DG) graphene nanoribbon field effect transistor (GNRFET) based sensors for high-performance DNA and gas detection are proposed through a simulation-based study.
Abstract: In this paper, new sensors based on a double-gate (DG) graphene nanoribbon field-effect transistor (GNRFET), for high-performance DNA and gas detection, are proposed through a simulation-based study. The proposed sensors are simulated by solving the Schrodinger equation using the mode space non-equilibrium Green’s function formalism coupled self-consistently with a 2D Poisson equation under the ballistic limits. The dielectric and work function modulation techniques are used for the electrical detection of DNA and gas molecules, respectively. The behaviors of both the sensors have been investigated, and the impacts of variation in geometrical and electrical parameters on the sensitivity of sensors have also been studied. In comparison to other FET-based sensors, the proposed sensors provide not only higher sensitivity but also better electrical and scaling performances. The obtained results make the proposed DG-GNRFET-based sensors as promising candidates for ultra-sensitive, small-size, low-power and reliable CMOS-based DNA, and gas sensors.
TL;DR: The excellent performance of this new device design is further demonstrated by incorporating the phototransistors into a sensor array to successfully image a star pattern.
Abstract: Flexible organic phototransistors are fabricated using polylactide (PLA), a polar bio-material, as the dielectric material. The charge trapping effect induced by the polar groups of the PLA layer leads to a photosensitivity close to ≈104. The excellent performance of this new device design is further demonstrated by incorporating the photo-transistors into a sensor array to successfully image a star pattern.
TL;DR: In this article, a GaN vertical trench metal-oxide-semiconductor field effect transistor (MOSFET) with normally off operation was reported, with a threshold voltage of 4.8 V, blocking voltage of 600 V at gate bias of 0 V, and on-resistance of $1.7~\Omega $ (10 V).
Abstract: This letter reports a GaN vertical trench metal–oxide–semiconductor field-effect transistor (MOSFET) with normally-off operation. Selective area regrowth of n+-GaN source layer was performed to avoid plasma etch damage to the p-GaN body contact region. A metal-organic-chemical-vapor-deposition (MOCVD) grown AlN/SiN dielectric stack was employed as the gate “oxide”. This unique process yielded a 0.5-mm2-active-area transistor with threshold voltage of 4.8 V, blocking voltage of 600 V at gate bias of 0 V, and on-resistance of $1.7~\Omega $ at gate bias of 10 V.
TL;DR: This work defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra high frequency circuits.
Abstract: Graphene is a promising candidate in analog electronics with projected operation frequency well into the terahertz range. In contrast to the intrinsic cutoff frequency (fT) of 427 GHz, the maximum oscillation frequency (fmax) of graphene device still remains at low level, which severely limits its application in radio frequency amplifiers. Here, we develop a novel transfer method for chemical vapor deposition graphene, which can prevent graphene from organic contamination during the fabrication process of the devices. Using a self-aligned gate deposition process, the graphene transistor with 60 nm gate length exhibits a record high fmax of 106 and 200 GHz before and after de-embedding, respectively. This work defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra high frequency circuits.