Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TLDR
In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.Abstract:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.read more
Citations
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Mixedmode Circuit Simulation of Silicon and Germanium Nanowire MOSFETs
TL;DR: In this paper, various parameters determining the behavior of device in the analog/digital circuits are studied and compared for Nanowire MOSFETs with Si and Ge as channel material.
Journal ArticleDOI
Impacts of NBTI and hot-carrier stress on silicon nanowire transistor characteristics
DasSanghamitra,DeySuprava,DashTara Prasanna,MohapatraEleena,JenaJhansi Rani,MaitiChinmay Kumar +5 more
TL;DR: Following the downscaling road map for planar metaloxide-semiconductor field effect transistors, non-planar (three-dimensional) multiple-gate architectures are becoming essential for the ultimate...
Journal ArticleDOI
Behavior of incorporated nitrogen in plasma-nitrided silicon oxide formed by chemical vapor deposition
TL;DR: In this article, the behavior of nitrogen atoms in a SiO2 film formed by chemical vapor deposition (CVD) was characterized by physical analysis and from electrical properties, and the changes in the chemical bonding and distribution of N in plasma-nitrided silicon oxide were investigated for different subsequent processes.
DissertationDOI
Conformal Deposition of Metal Silicide Layer on Si Wafer for Transistor Technology via a Molecular Approach
TL;DR: Zusammenfassung et al. as mentioned in this paper proposed a method for metal-silicon alloys in microelectronics via a molecular approach, which achieved low temperature Wet Conformal Nickel Silicide Deposition for Transistor Technology via a Molecular Approach.
Journal ArticleDOI
Improvement of On-cell Metrology Using Spectral Imaging with TCAD Modeling
Byung-Hoon Ahn,Kwang-Hoon Lee,Jaehun Yang,Jiseong Doh,Jae-hoon Jeong,T.G Kwag,Minseok Kim,Yeonjeong Kim,Jongchul Kim,Hyung Keun Yoo,Dae Sin Kim +10 more
TL;DR: In this paper , a TCAD model is used to augment the structural parameter and corresponding simulation spectrum for on-cell metrology based on spectral imaging (SI) with TCAD modeling for measuring advanced logic devices.
References
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Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.