Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TLDR
In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.Abstract:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.read more
Citations
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Journal ArticleDOI
Ge/Si core/shell nanowires with controlled low temperature grown Si shell thickness
Tomohiro Noguchi,Koudai Morita,Marolop Simanullang,Zhengyu Xu,Koichi Usami,Yukio Kawano,Tetsuo Kodera,Shunri Oda +7 more
TL;DR: In this paper, the authors used Si2H6 gas as a Si CVD source to form ultrathin layer of epitaxial Si film onto very narrow Ge nanowires.
Posted Content
Surface-Roughness-Limited Mean Free Path in Si Nanowire FETs
Hyo-Eun Jung,Mincheol Shin +1 more
TL;DR: In this paper, the mean free path (MFP) in silicon nanowire field effect transistors limited by surface roughness scattering (SRS) is calculated with the non-equilibrium Green's function method.
Journal ArticleDOI
Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical Insight
TL;DR: In this article , an area-scale tunneling technique was proposed to improve the performance of a nanosheet field effect transistor (NSFET) at a 5-nm technology node.
Journal ArticleDOI
Characteristics and Fluctuation of Negative Bias Temperature Instability in Si Nanowire Field-Effect Transistors
Runsheng Wang,Ru Huang,Yandong He,Zhenhua Wang,Gaosheng Jia,Dong-Won Kim,Donggun Park,Yangyuan Wang +7 more
TL;DR: In this paper, negative bias temperature instability (NBTI) in silicon nanowire field effect transistors (SNWFETs) is investigated and found to exhibit some new characteristics that are probably due to the structural nature of nanowires.
Journal ArticleDOI
Geometrical and band-structure effects on phonon-limited hole mobility in rectangular cross-sectional germanium nanowires
TL;DR: In this paper, the phonon-limited hole mobility in rectangular cross-sectional germanium nanowires was investigated, and a tight-binding approximation was used for holes, and phonons were described by a valence force field model.
References
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Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.