Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TLDR
In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.Abstract:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.read more
Citations
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Journal ArticleDOI
Noise and Device Parameters Sensitivity Analysis of Multi-Peak-Gaussian Doped 4H-SiC Junctionless FET (MG-4H-SiC-JLFET)
Journal ArticleDOI
Análisis termo-eléctrico de elementos finitos (EF) en vías de cobre nanométricas bajo tensión de alta fluencia
TL;DR: In this article, a thermal-electrical finite element (FE) model was developed to analyze failure mechanisms responsible of physical degradation (void, copper silicate formation, etc.) caused by high fluence stress of 90nm copper vias for FinfET devices.
III-V NanowiresVExtending a Narrowing Road Desirable transport properties appear to be important factors for extending the use of scaled semiconductor devices.
TL;DR: In this article, the authors give an overview of the field and summarize state-of-the-art for III-V nanowire devices, showing that the growth and processing technologies are maturing and that devices with good transistor characteristics are being fabricated by a combined bottom-up and top-down approach.
Proceedings ArticleDOI
Impacts of diameter-dependent annealing on S/D extension random dopant fluctuations in silicon nanowire MOSFETs
TL;DR: In this article, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon MOSFETs are investigated, in terms of electrostatic properties, source/drain series resistance (R SD ), and driving current.
Advanced Gate-All-Around Fin-Like Poly-Si TFTs With Multiple Nanowire Channels
Shih Wei Tu,Ta Chuan Liao,Wei-Kai Lin,Cheng Chin Liu,Ya-Hsiang Tai,Huang-Chung Cheng,Feng Tso Chien,Chii Wen Chen,Wan Lu Chen +8 more
TL;DR: The gate-all-around (GAA) fin-like poly-Si TFTs with multiple nanowire channels (MNCs) have been fabricated using a simple process to demonstrate high performance electrical characteristics as mentioned in this paper.
References
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High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.