Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TLDR
In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.Abstract:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.read more
Citations
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Reduction of the self-forces in Monte Carlo simulations of semiconductor devices on unstructured meshes
TL;DR: The progress in minimisation of the self-forces on arbitrary meshes is reported on by showing that they can be greatly reduced on a finite element mesh with proper interpolation functions and included into a self-consistent finite element 3D Monte Carlo device simulator.
Journal ArticleDOI
Gate-induced switching and negative differential resistance in a single-molecule transistor: emergence of fixed and shifting states with molecular length.
Amir A. Farajian,Rodion V. Belosludov,Hiroshi Mizuseki,Yoshiyuki Kawazoe,Tomihiro Hashizume,Boris I. Yakobson +5 more
TL;DR: The results show that proper functional molecules can be used in conjunction with metallic electrodes to achieve basic electronics functionality at molecular length scales.
Journal ArticleDOI
Influences of silicon nanowire morphology on its electro‐optical properties and applications for hybrid solar cells
Hong-Jhang Syu,Shu-Chia Shiu,Yung-Jr Hung,Chen-Chih Hsueh,Tzu-Ching Lin,Thiyagu Subramani,San-Liang Lee,Ching-Fuh Lin +7 more
TL;DR: In this article, the morphology, optical, and electrical properties of silicon nanowire (SiNW) arrays and their applications on inorganic/organic hybrid solar cells were investigated, and two kinds of metal-assisted chemical etching (MacEtch) processes were used to obtain SiNW arrays.
Journal ArticleDOI
Spice Modeling of Silicon Nanowire Field-Effect Transistors for High-Speed Analog Integrated Circuits
TL;DR: In this paper, the authors present the fully depleted BSIMSOI modeling of low power NMOS and PMOS SGFETs with 10 nm channel length and 2 nm channel radius, extraction of distributed device parasitics, and measuring the capabilities of these transistors for high-speed analog and RF applications.
Journal ArticleDOI
Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design
TL;DR: In this paper, various configurations of double-gate MOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID) design.
References
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Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.