Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TLDR
In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.Abstract:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.read more
Citations
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Journal ArticleDOI
Advantages of silicon nanowire metal-oxide-semiconductor field-effect transistors over planar ones in noise properties
W. Feng,R. Hettiarachchi,Soshi Sato,Kuniyuki Kakushima,Masaaki Niwa,Hiroshi Iwai,Keisaku Yamada,Kenji Ohmori +7 more
TL;DR: In this paper, the authors investigated the low-frequency noise behavior of silicon nanowire metal-oxide-semiconductor field effect transistors (NWFETs) by comparison with that of a planar FET.
Journal ArticleDOI
Perspective of flash memory realized on vertical Si nanowires
TL;DR: The memory devices with highly scaled single-crystal Si nanowire (SiNW) channel and a gate-all-around (GAA) structure achieve superior program/erase (P/E) speed, cycling and high-temperature retention characteristics as compared to the planar one and are considered as promising candidate for future ultra-high non-volatile flash memory application.
Semiconductor nanowire growth and integration
TL;DR: In this article, the authors investigated the properties of nanowires that can be advantageous, such as small diameters, large surface area and smooth surfaces of the nanowire materials.
Journal ArticleDOI
Evaluation of controlled strain in silicon nanowire by UV Raman spectroscopy
Ryo Yokogawa,Shuichiro Hashimoto,Shuhei Asada,Motohiro Tomita,Motohiro Tomita,Takanobu Watanabe,Atsushi Ogura +6 more
TL;DR: In this paper, the strain states in Si nanowires formed by different oxidation processes were evaluated by UV Raman spectroscopy and they confirmed that a higher tensile strain was induced by the partial presence of a tetraethyl orthosilicate (TEOS) SiO2 layer prior to the thermal oxidation.
Journal ArticleDOI
Interfacial reaction-dominated full oxidation of 5 nm diameter silicon nanowires
Ilsoo Kim,Tae Eon Park,Ki-Young Lee,Ryong Ha,Byung-Hyun Kim,Byung-Hyun Kim,Yong-Chae Chung,Kwang-Ryeol Lee,Heon Jin Choi +8 more
TL;DR: In this paper, the authors investigated the self-limiting oxidative behavior of Si nanowires with diameters of 5'nm and compared their findings with those for SiNWs with diameter of 30'nm.
References
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Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.