Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TLDR
In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.Abstract:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.read more
Citations
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Journal ArticleDOI
1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor
Jae Woo Lee,Moon Ju Cho,Eddy Simoen,Romain Ritzenthaler,M. Togo,Guillaume Boccardi,Jerome Mitard,Lars-A. ˚ke Ragnarsson,Thomas Chiarella,Anabela Veloso,Naoto Horiguchi,Aaron Thean,Guido Groeseneken +12 more
TL;DR: In this paper, the origin of performance difference between gate-first (GF) and replacement metal gate (RMG) fin field effect transistors (FinFETs) is investigated.
Journal ArticleDOI
TCAD study on gate-all-around cylindrical (GAAC) transistor for CMOS scaling to the end of the roadmap
TL;DR: TCAD study on gate-all-around cylindrical (GAAC) transistor for sub-10-nm scaling is reported and the GAAC transistor device physics, TCAD simulation, and proposed fabrication procedure have been discussed.
Journal ArticleDOI
Analytical modeling of the lattice and thermo-elastic coefficient mismatch-induced stress into silicon nanowires horizontally embedded on insulator-on-silicon substrates
TL;DR: In this article, an analytical model has been developed to estimate the amount of induced stress in nanowires which are horizontally embedded with different fractions within an Insulator-on-Silicon substrate.
Proceedings ArticleDOI
Modeling of stress-retarded orientation-dependent oxidation: shape engineering of silicon nanowire channels
Fa-Jun Ma,S.C. Rustagi,Hui Zhao,Ganesh S. Samudra,Navab Singh,K. D. Budhaaraju,Guo-Qiang Lo,Dim-Lee Kwong +7 more
TL;DR: In this article, a universal stress retardation parameter set is proposed to account for initial oxidation rate enhancement, orientation-dependent retardation and self-limiting phenomena observed in the dry oxidation experiment of the silicon FIN nanostructures over a wide temperature range.
Journal ArticleDOI
Ta2Ni3Se8: 1D van der Waals Material with Ambipolar Behavior
Kyung Hwan Choi,Byung Joo Jeong,Jiho Jeon,You Kyoung Chung,Dongchul Sung,Sang Ok Yoon,Sudong Chae,Bum Jun Kim,Seungbae Oh,Sang Hoon Lee,Chaeheon Woo,Xue Dong,Asghar Ghulam,Junaid Ali,Tae Yeong Kim,Minji Seo,Jae-Hyun Lee,Joonsuk Huh,Hak Ki Yu,Jae-Young Choi +19 more
TL;DR: In this article, a field-effect transistor is successfully fabricated on mechanically exfoliated Ta2 Ni3 Se8 nanowires, which exhibit ambipolar semiconducting behavior with maximum mobilities of 20.3 and 3.52 cm2 V-1 s-1 for electrons and holes, respectively.
References
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Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.