Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TLDR
In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.Abstract:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.read more
Citations
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Journal ArticleDOI
The top-down fabrication of a 3D-integrated, fully CMOS-compatible FET biosensor based on vertically stacked SiNWs and FinFETs
Elizabeth Buitrago,Montserrat Fernandez-Bolanos,Sara Rigante,Christian F. Zilch,Nicole S. Schröter,Adrian M. Nightingale,Adrian M. Ionescu +6 more
TL;DR: A 3D vertically stacked silicon nanowire (SiNW) and Fin field effect transistor (FET) has been successfully fabricated for the first time by a top-down, complementary metal oxide semiconductor (CMOS) compatible process on silicon on insulator (SOI) substrates for biosensing applications as discussed by the authors.
Journal ArticleDOI
Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs
TL;DR: In this paper, the impact of an advanced shell doping profile (SDP) on the electrical characteristics of a junctionless FET in terms of OFF-current, subthreshold swing (SS), and ON-current by a numerical simulator is presented.
Journal ArticleDOI
Diameter dependence of electron mobility in InGaAs nanowires
Jared J. Hou,Fengyun Wang,Ning Han,Haoshen Zhu,KitWa Fok,WaiChak Lam,SenPo Yip,TakFu Hung,Joshua E.-Y. Lee,Johnny C. Ho +9 more
TL;DR: In this paper, the diameter dependent electron mobility study of InGaAs nanowires (NWs) grown by gold-catalyzed vapor transport method was presented, which suggests a careful design consideration of nanowire dimension is required for achieving the optimal device performances.
Journal ArticleDOI
High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure
Szu-Hung Chen,Wen-Shiang Liao,Hsin-Chia Yang,Shea-Jue Wang,Yue-Gie Liaw,Hao-Hao Wang,Haoshuang Gu,Mu-Chun Wang +7 more
TL;DR: The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade.
Journal ArticleDOI
Monolayer Hexagonal Boron Nitride Tunnel Barrier Contact for Low-Power Black Phosphorus Heterojunction Tunnel Field-Effect Transistors.
TL;DR: This work reports a black phosphorus (BP) heterojunction (HJ) TFET that exhibits a record high I60 and demonstrates the influence of the tunnel barrier contact on device performance, paving the way for the development of ultrafast low-power logic circuits beyond CMOS capabilities.
References
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Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.