Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TLDR
In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.Abstract:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.read more
Citations
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Journal ArticleDOI
Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET
Yunho Choi,Kitae Lee,Kyoung Yeon Kim,Sihyun Kim,Junil Lee,Ryoongbin Lee,Hyun-Min Kim,Young Suh Song,Sangwan Kim,Jong-Ho Lee,Byung-Gook Park +10 more
TL;DR: In this paper, the authors investigated the effect of Si parasitic channel height on the electrical characteristics of stacked nanosheet GAA FETs by using technology computer aided design (TCAD) simulation.
Journal ArticleDOI
Integrated modeling of Self-heating of confined geometry (FinFET, NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits
TL;DR: This paper combines theoretical modeling and systematic transistor characterization to extract thermal parameters at the transistor level to demonstrate the importance of multi-time constant thermal circuits to predict the spatio-temporal SHE in modern sub-20 nm transistors.
Journal ArticleDOI
Impurity-limited mobility and variability in gate-all-around silicon nanowires
TL;DR: In this paper, the scattering of electrons and holes by charged dopant impurities in gate-all-around silicon nanowires (Si NWs) with diameters in the 2-8nm range is discussed.
Journal ArticleDOI
Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors
Y. Wang,Talib Al-Ameri,Xingsheng Wang,Vihar P. Georgiev,Ewan Towie,Salvatore Maria Amoroso,Andrew R. Brown,Binjie Cheng,David Reid,Craig Riddet,Lucian Shifren,Saurabh Sinha,Greg Yeric,Robert Campbell Aitken,Xiaoyan Liu,Jinfeng Kang,Asen Asenov +16 more
TL;DR: In this article, the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies has been investigated based on 3D drift-diffusion simulations in 2D cross sections along the direction of the transport.
Journal ArticleDOI
Tellurium Nanowire Gate-All-Around MOSFETs for Sub-5 nm Applications.
Yiheng Yin,Zhaofu Zhang,Hongxia Zhong,Chen Shao,Xuhao Wan,Can Zhang,John Robertson,John Robertson,Yuzheng Guo +8 more
TL;DR: In this article, the authors conduct a co-conducting study on the gate-all-around (GAA) and nanowire (NW) technologies and show that they are the ultimate solutions to sustain Moore's law benefitting from the exceptional gate control ability.
References
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Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.