Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TLDR
In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.Abstract:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.read more
Citations
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Journal ArticleDOI
InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments
Adam Burke,Adam Burke,Damon J. Carrad,J.G. Gluschke,Kristian Storm,S. Fahlvik Svensson,Heiner Linke,Lars Samuelson,Adam P. Micolich +8 more
TL;DR: A method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments with excellent scalability potential makes them highly favorable for the development of advanced nanowires devices and possible integration with vertical wrap- gates in 3Dnanowire network architectures.
Journal ArticleDOI
Nanostructures for medical diagnostics
TL;DR: In this article, the authors focus on the application of various nanostructures and nanodevices in clinical diagnostics and detection of important biological molecules, and discuss the prospects, benefits, and limitations of using these novel techniques in the fields of biodetection and medical diagnostics.
Journal ArticleDOI
Silicon nanowire pH sensors fabricated with CMOS compatible sidewall mask technology
TL;DR: In this paper, a CMOS compatible sidewall mask technology (SMT) was proposed for top-down fabrication of SiNWs and a highly sensitive pH sensor based on SiNW FETs.
Journal ArticleDOI
Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs
TL;DR: In this article, the effects of nanowire line edge roughness (LER) in gate-all-around silicon MOSFETs are comprehensively investigated through 3-D statistical simulation.
Journal ArticleDOI
Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach
K.D. Buddharaju,Navab Singh,S.C. Rustagi,Selin H. G. Teo,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +6 more
TL;DR: In this article, the integration potential of gate-all-around (GAA) Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is demonstrated.
References
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High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
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FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.