Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TLDR
In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.Abstract:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.read more
Citations
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Journal ArticleDOI
Effective passivation and high-performance metal–oxide–semiconductor devices using ultra-high-vacuum deposited high-κ dielectrics on Ge without interfacial layers
L.K. Chu,R.L. Chu,T. D. Lin,W.C. Lee,C.A. Lin,M.L. Huang,Y. J. Lee,J. Kwo,J. Kwo,Minghwei Hong +9 more
TL;DR: In this article, the oxide/Ge interfaces have been studied chemically, structurally, and electronically: hetero-structures of all the studied oxides on Ge are highly thermally stable with annealing to 500°C, and their interfaces remain atomically sharp.
Journal ArticleDOI
Intrinsic Tolerance to Total Ionizing Dose Radiation in Gate-All-Around MOSFETs
Everett Comfort,Martin Rodgers,William Allen,Steve Gausepohl,En Xia Zhang,Michael L. Alles,Harold L. Hughes,P.J. McMarr,Ji Ung Lee +8 more
TL;DR: In this paper, the authors measured the total ionizing dose response of gate-all-around silicon nanowire n-and pMOSFETs to x-ray doses up to 2Mrad(SiO2), and they showed that they are radiation hard, with no degradation in threshold voltage, off-state current, or subthreshold slope, even at the highest dose for a wide range of bias conditions.
Journal ArticleDOI
Junctionless Gate-All-Around pFETs Using In-situ Boron-Doped Ge Channel on Si
TL;DR: In this paper, the authors proposed a gate-all-around junctionless device with channel doping of 5 × 1018 cm−3, fin width of 27 nm, and gate length of 250 nm.
Journal ArticleDOI
Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage
Tingting Liu,Tingting Liu,Jianwen Zhao,Weiwei Xu,Junyan Dou,Xinluo Zhao,Wei Deng,Changting Wei,Wenya Xu,Wenrui Guo,Wenming Su,Jiansheng Jie,Zheng Cui +12 more
TL;DR: A novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) to have high ON currents, high dark-to-bright current ratios and good stability under repeated white light illumination.
Journal ArticleDOI
Unified Compact Model for Nanowire Transistors Including Quantum Effects and Quasi-Ballistic Transport
TL;DR: In this paper, a surface potential-based compact model for nanowire FETs is presented, which considers 1-D electrostatics along with the effect of multiple energy subbands.
References
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Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.