Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TLDR
In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.Abstract:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.read more
Citations
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Journal ArticleDOI
Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs
TL;DR: In this article, a gate-all-around (GAA) poly-Si FET using sidewall damascene method is successfully demonstrated, which exhibits superior electrical characteristics including higher on-state current of 40μA/μm (n-type) and 26μA /μm(p-type), steep subthreshold swing of 82mV/dec.
Journal ArticleDOI
Hydrodynamic modeling of electron transport in gated silicon nanowires transistors
TL;DR: In this article, the authors present a theoretical study of low-field electron mobility in rectangular gated silicon nanowire transistors at 300 K based on a hydrodynamic model and the self-consistent solution of the Schrodinger and Poisson equations.
Journal ArticleDOI
Convex corner induced capacitance–voltage response from depletion to deep depletion in non-planar substrate metal-oxide-semiconductor capacitors with ultra thin oxide
Po-Hao Tseng,Jenn-Gwo Hwu +1 more
TL;DR: In this article, the convex corner induced capacitance responses from depletion to deep depletion regions in non-planar substrate metal-oxide-semiconductor (MOS) capacitors with ultra thin oxides are comprehensively studied.
Proceedings ArticleDOI
Correlation Effects in Silicon Nanowire MOSFETs
TL;DR: In this paper, a numerical study of the self-energy correction due to correlation effects from dynamic screening of the moving electron in silicon nanowire transistors is presented, which is then incorporated self-consistently into a nonequilibrium Green's function (NEGF) code.
Proceedings ArticleDOI
An extensive analysis of In 0.53 Ga 0.47 As/InP surrounding gate MOSFET to enhance the electrostatic performance using $\delta$ -doped technique
TL;DR: In this paper, the authors presented an investigation of source $\delta$ -doped In 0.53 Ga 0.47 As /InP based SGHMOSFET to enhance the device performance.
References
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Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.