Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Journal ArticleDOI
Implementation of High speed and Low power 6T SRAM cell using FinFET at 22nm technology
A.Sai Kumar,B.S. Priyanka Kumari +1 more
TL;DR: The total leakage of FinFET SRAM cell is reduced by 23% after applying self controllable voltage level technique and the power consumption and write delay as well as read delay of proposed 6T FinFet based SRam cell structure improves on CADENCE VIRTUOSO tool at 22nm technology scale.
Proceedings ArticleDOI
A novel flow for reducing clock skew considering NBTI effect and process variations
Jifeng Chen,Mohammad Tehranipoor +1 more
TL;DR: An extended “divide and conquer” algorithm is developed to identify the critical clock buffers for replacement and can effectively reduce the clock skew by at least 20% by replacing only 1.08% clock buffers on average for 10 years of degradation, even under an extremely constrained condition.
Proceedings ArticleDOI
A wakeup rush current and charge-up time analysis method for programmable power-gating designs
Kaijian Shi,Jingsong Li +1 more
TL;DR: A chain latency annotation method is presented in this paper to model the chain configurations and programmable main-chain turn-on time of complex power-gating designs in the wakeup rush current and charge-up time analysis.
Journal ArticleDOI
Leakage power reduction techniques of 45 nm static random access memory (SRAM) cells
TL;DR: In this article, the leakage current, static noise margin, and read current of SRAM cells, based on the UMC 45 nm complementary metaloxide-semiconductor (CMOS) process with leakage current reduction techniques has been simulated.
Proceedings ArticleDOI
Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier
TL;DR: A reconfigurable TIM is designed with an adjustable resolution range of 15 down to 0.5 ps and a measurement dynamic range of 480 to 16 ps to perform a variety of time related measurements which require different test specifications.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.