Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Journal ArticleDOI
Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors
Yoongu Kim,Ross Daly,Jeremie S. Kim,Chris Fallin,Ji-Hye Lee,Donghyuk Lee,Christopher B. Wilkerson,Konrad K. Lai,Onur Mutlu +8 more
TL;DR: This paper exposes the vulnerability of commodity DRAM chips to disturbance errors, and shows that it is possible to corrupt data in nearby addresses by reading from the same address in DRAM by activating the same row inDRAM.
Proceedings ArticleDOI
An integrated GPU power and performance model
Sunpyo Hong,Hyesoon Kim +1 more
TL;DR: An integrated power and performance prediction model for a GPU architecture to predict the optimal number of active processors for a given application and the outcome of IPP is used to control the number of running cores.
Journal ArticleDOI
Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors
TL;DR: In this paper, a detailed theoretical model for the physics of strain effects in bulk semiconductors and surface Si, Ge, and III-V channel metal-oxide-semiconductor field effect transistors is presented.
Journal ArticleDOI
Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies
TL;DR: This paper analyzes the read stability N-curve metrics and compares them with the commonly used static noise margin (SNM) metric defined by Seevinck, and demonstrates that the new metrics provide additional information in terms of current, which allows designing a more robust and stable cell.
Proceedings ArticleDOI
Compact thermal modeling for temperature-aware design
TL;DR: Results from the thermal model show that a temperature-aware design approach can provide more accurate estimations, and therefore better decisions and faster design convergence.
References
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High-speed semiconductor devices
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Proceedings ArticleDOI
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks
TL;DR: Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.
Proceedings ArticleDOI
A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation
TL;DR: In this paper, a dynamic threshold voltage MOSFET (DTMOS) was proposed to extend the lower bound of power supply to ultra-low voltages (06 V and below).
Proceedings ArticleDOI
Technology and design challenges for low power and high performance
Vivek De,Shekhar Borkar +1 more
TL;DR: Key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance are discussed, with particular focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage.
MOS Scaling: Transistor Challenges for the 21st Century
TL;DR: In this paper, the authors quantified key scaling limits for MOS transistors and showed that traditional SiO2 gate dielectrics will reach fundamental leakage limits, due to tunneling, for an effective electrical thickness below 2.3 nm.