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Journal ArticleDOI

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Kaushik Roy, +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Abstract
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

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Citations
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Proceedings ArticleDOI

A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits

TL;DR: A new transistor-level layout generation strategy makes possible to design static CMOS cells for any logic function on demand, allowing a logic minimization without any logic constraints.
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Load Balancing on Dynamic Network Using Mobile Process Groups

TL;DR: A modified version of diffusion algorithm for load balancing on dynamic networks is proposed using the framework of mobile agent groups for reliable and coordinated communication amongst the agents participating in load balancing.
Proceedings ArticleDOI

Fault models for embedded-DRAM macros

TL;DR: This paper starts from an standard SRAM test algorithm and discusses the faults which are not covered in the SRAM testing but should be considered in the DRAM testing, and studies the behavior of those faults and the tests which can detect them.
Proceedings ArticleDOI

First level hold: a novel low-overhead delay fault testing technique

TL;DR: This paper proposes using supply gating at the first level of logic gates to hold the state of the combinational circuit in a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay faultTesting with significantly less design overhead.
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Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches

TL;DR: This work proposes a new power-gating technique that is tolerant to process variations and scalable to more than more than two intermediate power-off modes, which requires less design effort and offers greater power reduction and smaller area cost than the previous method.
References
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Journal ArticleDOI

Design of ion-implanted MOSFET's with very small physical dimensions

TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book

Fundamentals of Modern VLSI Devices

Yuan Taur, +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Book

Physics and technology of semiconductor devices

TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book

Digital Integrated Circuits

TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.
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