Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Efficient Runtime Management of Reconfigurable Hardware Resources
TL;DR: This dissertation addresses three major problems related to hardware resources runtime management: efficient online hardware task scheduling and placement, power consumption reduction and reconfiguration overhead minimization, and a novel logic element with lower power consumption compared to current approaches.
Leakage aware digital design optimization for minimal total power consumption in nanometer CMOS technologies
TL;DR: In this article, the authors investigate the influence of static power on the design methodologies for low power, in particular, the effects of architectural as well as technology modifications are explored.
Proceedings ArticleDOI
Design of low leakage power SRAM using multithreshold technique
J B V Subramanyam,S. Syed Basha +1 more
TL;DR: The proposed device is applied using different techniques for leakage reduction namely gated Vdd and multithreshold voltage techniques to reduce leakage and therefore, leakage power in the SRAM cell is decreased and provides better performance.
Journal ArticleDOI
Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs
TL;DR: A novel circuit-level GOS model is proposed which provides a higher accuracy of its dc characteristics than any of the previous models and being is able to represent a minimum-size GOS-impacted MOSFET.
Proceedings ArticleDOI
An improved domino logic
Nagendra Sah,Eesh Mittal +1 more
TL;DR: This paper has proposed a new circuit in order to improve the power consumption by applying a multi-threshold technique and Simulations are done in Cadence for 90nm with IBM technology for OR gates with supply voltage of 1v.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.