Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Journal ArticleDOI
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits
Paulo F. Butzen,Leomar S. da Rosa,Erasmo J. D. Chiappetta Filho,Andre I. Reis,Renato P. Ribas +4 more
TL;DR: A novel leakage current estimation method, which takes into account the dependency of leakage mechanisms, is proposed for general CMOS complex gates, including non-series-parallel transistor arrangements, not covered by existing approaches.
Journal ArticleDOI
Static NBTI Reduction Using Internal Node Control
TL;DR: It is proved that the INC selection problem is NP-complete and a linear-time heuristic that can quickly determine near-optimal placements is presented that can reduce static NBTI-induced delay over a ten year period by 30--60% and can reduce total path delay by an average 9.4% when NBTi degradation is severe.
Patent
Tunnel field effect transistor (tfet) with lateral oxidation
Jack C. Lee,Han Zhao +1 more
TL;DR: In this article, a verticalmode tunnel field effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region, which operates to reduce tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET.
Journal ArticleDOI
Extremely scaled high-k/In0.53Ga0.47As gate stacks with low leakage and low interface trap densities
TL;DR: In this paper, a pre-deposition technique consisting of alternating cycles of nitrogen plasma and tetrakis(dimethylamino)titanium was proposed for high-k/III-V gate dielectric stacks with extremely high accumulation capacitance densities.
A Circuit-Compatible Model of Ballistic Carbon
TL;DR: In this paper, a circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit is presented, where both the I-V and the C-V characteristics of the device have been efficiently modeled for circuit simulations.
References
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Yuan Taur,Tak H. Ning +1 more
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TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.