Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Proceedings ArticleDOI
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs
TL;DR: A programmable wakeup architecture for DCPG FPGAs that ensures that a power-gated module can be turned on such that the wakeup current constraints are not violated and the area and power overheads are studied.
Proceedings ArticleDOI
CNTFET-based design of dynamic ternary full adder cell
TL;DR: In this paper, a novel CNTFET-based design of ternary full adder (TFA) cell using dynamic logic style is proposed, which is designed based on the conventional CMOS architecture with utilization of inherent binary nature (0, 1) of input carry signal.
Proceedings ArticleDOI
Dual diode-Vth reduced power gating structure for better leakage reduction
TL;DR: In this article, an alternative dual diode-Vth reduced power gating structure is proposed for better reduction of leakage currents, especially for low-power, high-performance portable devices.
Journal ArticleDOI
Low leakage domino logic circuit for wide fan-in gates using CNTFET
Sandeep Garg,Tarun Kumar Gupta +1 more
TL;DR: The CNTFET technology is discussed that has faster switching speed and high-carrier mobility as compared with the CMOS technology and a new technique ultra-low power dynamic node driven transistor domino Logic is proposed for designing low-power domino logic circuits.
Proceedings ArticleDOI
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
TL;DR: The experimental studies show that the proposed energy recovery designs can be used to reduce the energy consumption by about 30% while provide a better reliability (comparable to what is achievable from fault tolerance techniques) as compared to conventional pipelined interconnects.
References
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TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
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Yuan Taur,Tak H. Ning +1 more
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Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.