Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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VLSI-SOC: From Systems to Chips : IFIP TC 10/WG 10.5, Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1 - 3, 2003, Darmstadt, Germany
TL;DR: In this paper, the authors present a generic approach for on-chip communication, testing and debugging of SoCs, including the integration of Coarse-grained Reconfigurable XPP-Arrays into pipelined Risc Processor Datapath.
Proceedings ArticleDOI
High temperature analog circuit design in PD-SOI CMOS technology using reverse body biasing
TL;DR: It is demonstrated that the reverse body biasing (RBB) approach improves the transistor's analog performance up to 400°C and operation in the lower moderate inversion region of the SOI transistor is feasible at increased temperatures.
Journal ArticleDOI
Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches
TL;DR: A signature analysis technique to efficiently test power-gating structures that provide intermediate power-off modes is proposed and, based on this technique, a methodology to repair catastrophic and parametric faults, and to tolerate process variations is presented.
Proceedings ArticleDOI
Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions
Swarup Bhunia,Kaushik Roy +1 more
TL;DR: An overview of major low-power and variation-tolerant design techniques is provided; related test issues are discussed and effectiveness of self-calibration/self-repair solutions to maintain high yield while achieving low power dissipation is focused on.
Proceedings ArticleDOI
A MOS transistor array with pico-ampere order precision for accurate characterization of leakage current variation
TL;DR: In this paper, a transistor array design for accurate sub-threshold current measurement is proposed, which achieves both compact layout area and pico-ampere order precision, which is particularly useful in off-state current variation characterization.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.